Frank K. Gürkaynak

Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook

This article provides a pragmatic survey on the state of the art in GALS architectural techniques, design flows, and applications. The authors also prescribe several industrial inventions and changes in methodology, tools, and design flow that would improve GALS-based integration of IP blocks.

Self-timed ring for globally-asynchronous locally-synchronous systems

The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) techniques to SoC design. We have implemented on a VLSI test chip three alternative solutions to fill the gap: an arbitrated bus, a switch, and a self-timed ring. Circuit details and various extensions of the basic ring structure are also being discussed. These include bypassing ring transceivers to free the local islands from managing en route traffic and transceivers that inform the sender in case a defective receiver is unable to accept a data item. This is indispensable to prevent any deadlocks. For a ring with five nodes a total data throughput of 520 MegaDataPackets/s was achieved.

Efficient ASIC implementation of a real-time depth mapping stereo vision system

This paper presents a fast and area-efficient implementation of a real-time stereo vision algorithm for spatial depth mapping. The design combines two well-known area-based approaches to stereo matching and includes an occlusion detection method. Hardware efficiency is achieved by storing only partial images on-chip, avoiding full-sized frame buffers. A low-latency dataflow-oriented structure makes it possible to process 256/spl times/192 pixel. Input streams with a rate in excess of 50 frames per second, amounting to more than 54 million pixel /spl times/ disparity measurements per second (PDS) (for a 25-pixel disparity range), or roughly 18 GOPS. The design has been integrated in a 0.25 /spl mu/m standard CMOS technology and occupies an area of less than 3 mm/sup 2/.

Towards an AES crypto-chip resistant to differential power analysis

Differential power analysis (DPA) implies measuring the supply current of a cipher-circuit in an attempt to uncover part of a cipher-key. Cryptographic security gets compromised if the current waveforms so obtained correlate with those from a hypothetical power model of the circuit. Such correlations can be minimized by masking datapath operations with random bits in a reversible way. We analyze such countermeasures and discuss how they perform and how well they lend themselves to being incorporated into dedicated hardware implementations of the advanced encryption standard (AES) block cipher. Our favorite masking scheme entails a performance penalty of some 40-50%. We also present a VLSI design that can serve for practical experiments with DPA.

GALS at ETH Zurich: success or failure?

The Integrated Systems Laboratory (IIS) of ETH Zurich (Swiss Federal Institute of Technology) has been active in globally-asynchronous locally-synchronous (GALS) research since 1998. During this time, a number of GALS circuits have been fabricated and tested successfully on silicon. From a hardware designers point of view, this article summarizes the evolution from proof of concept designs over multi-point interconnects to applications that specifically take advantage of GALS operation to improve cryptographic security. In spite of the fact that they fail to address numerous idiosyncrasies of GALS (such as good partitioning into synchronous islands, port controller design, pausable clock generators, design for test, etc.), hierarchical design flows have been found to form a workable basis. What prevents GALS from gaining a wider acceptance mainly is the initial effort required to come up with a design flow that is efficient and dependable

Developing a hardware evaluation method for SHA-3 candidates

The U.S. National Institute of Standards and Technology encouraged the publication of works that investigate and evaluate the performances of the second round SHA-3 candidates. Besides the hardware characterization of the 14 candidate algorithms, the main goal of this paper is the description of a reliable methodology to efficiently characterize and compare VLSI circuits of cryptographic primitives. We took the opportunity to apply it on the ongoing SHA-3 competition. To this end, we implemented several architectures in a 90 nm CMOS technology, targeting high- and moderate-speed constraints separately. Thanks to this analysis, we were able to present a complete benchmark of the achieved post-layout results of the circuits.

A functional test methodology for globally-asynchronous locally-synchronous systems

In this paper, we present a high-level functional test methodology for GALS systems. In this new test methodology, the self-timed wrapper of a GALS module is enhanced by a test extension element that provides a unified interface to a centralized test controller. Each test extension element is customized for the locally-synchronous island it is attached to, and is able to decouple the asynchronous communication ports from the locally-synchronous islands in a test mode. The test controller can then issue a series of commands to the test extension elements to initiate data transfers between GALS modules. Testing is achieved by observing these data transfers through the test extension elements. We also introduce a simple design automation solution to customize both the test extension element and the test controller for the GALS system.

Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields

Elliptic curve cryptosystems (ECCs) are utilised as an alternative to traditional public-key cryptosystems, and are more suitable for resource-limited environments because of smaller parameter size. In this study, the authors carry out a thorough investigation of side-channel attack aware ECC implementations over finite fields of prime characteristic including the recently introduced Edwards formulation of elliptic curves. The Edwards formulation of elliptic curves is promising in performance with built-in resiliency against simple side-channel attacks. To our knowledge the authors present the first hardware implementation for the Edwards formulation of elliptic curves. The authors also propose a technique to apply non-adjacent form (NAF) scalar multiplication algorithm with side-channel security using the Edwards formulation. In addition, the authors implement Joyes highly regular add-always scalar multiplication algorithm both with the Weierstrass and Edwards formulation of elliptic curves. Our results show that the Edwards formulation allows increased area-time performance with projective coordinates. However, the Weierstrass formulation with affine coordinates results in the simplest architecture, and therefore has the best area-time performance as long as an efficient modular divider is available.

A generic standard cell design methodology for differential circuit styles

In this paper we present a generic methodology for the rapid generation and implementation of standard cell libraries for differential circuit design styles. We demonstrate a systematic approach for the classification of circuit topologies (footprints) and for generating the templates that correspond to a large number of functions. The generation of an extensive cell library with more than 4500 standard cells based on 19 footprints is demonstrated using a 180 nm CMOS technology.

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Near-sensor data analytics is a promising direction for internet-of-things endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data are stored or sent over the network at various stages of the analytics pipeline. Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues. To cope with the combined workload of analytics and encryption in a tight power envelope, we propose Fulmine, a system-on-chip (SoC) based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks. The Fulmine SoC, fabricated in 65-nm technology, consumes less than 20mW on average at 0.8V achieving an efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to 25MIPS/mW in software. As a strong argument for real-life flexible application of our platform, we show experimental results for three secure analytics use cases: secure autonomous aerial surveillance with a state-of-the-art deep convolutional neural network (CNN) consuming 3.16pJ per equivalent reduced instruction set computer operation, local CNN-based face detection with secured remote recognition in 5.74pJ/op, and seizure detection with encrypted data collection from electroencephalogram within 12.7pJ/op.