Fred Chen

Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors

This work introduces the use of compressed sensing (CS) algorithms for data compression in wireless sensors to address the energy and telemetry bandwidth constraints common to wireless sensor nodes. Circuit models of both analog and digital implementations of the CS system are presented that enable analysis of the power/performance costs associated with the design space for any potential CS application, including analog-to-information converters (AIC). Results of the analysis show that a digital implementation is significantly more energy-efficient for the wireless sensor space where signals require high gain and medium to high resolutions. The resulting circuit architecture is implemented in a 90 nm CMOS process. Measured power results correlate well with the circuit models, and the test system demonstrates continuous, on-the-fly data processing, resulting in more than an order of magnitude compression for electroencephalography (EEG) signals while consuming only 1.9 μW at 0.6 V for sub-20 kS/s sampling rates. The design and measurement of the proposed architecture is presented in the context of medical sensors, however the tools and insights are generally applicable to any sparse data acquisition.

Integrated circuit design with NEM relays

To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nano-electro-mechanical (NEM) relays. A dynamical Verilog-A model of the NEM relay is described and correlated to device measurements. Using this model we explore NEM relay design strategies for digital logic and I/O that can significantly improve the energy efficiency of the whole VLSI system. By exploiting the low effective threshold voltage and zero leakage achievable with these relays, we show that NEM relay-based adders can achieve an order of magnitude or more improvement in energy efficiency over CMOS adders with ns-range delays and with no area penalty. By applying parallelism, this improvement in energy-efficiency can be achieved at higher throughputs as well, at the cost of increased area. Similar improvements in high-speed I/O energy are also predicted by making use of the relays to implement highly energy-efficient digital-to-analog and analog-to-digital converters.

Low Programming Current Phase Change Memory Cell with Double GST Thermally Confined Structure

A novel PCM cell with double GST thermally confined structure was proposed and fabricated in this work. by inserting an extra bottom GST layer under the confined GST region, the heat loss can be effectively prevented and the temperature profile over active region becomes more uniform. thus, a low reset current less than 0.3 ma can be achieved and the set performance is also improved to be faster than 200 ns.

A signal-agnostic compressed sensing acquisition system for wireless and implantable sensors

A signal-agnostic compressed sensing (CS) acquisition system is presented that addresses both the energy and telemetry bandwidth constraints of wireless sensors. The CS system enables continuous data acquisition and compression that are suitable for a variety of biophysical signals. A hardware efficient realization of the CS sampling demonstrates data compression up to 40x on an EEG signal while maintaining low perceptual loss in the reconstructed signal. The proposed system also simultaneously relaxes the noise and resolution constraints of the analog front end (AFE) and ADC by nearly an order of magnitude. The CS sampling hardware is implemented in a 90 nm CMOS process and consumes 1.9 µW at 0.6 V and 20 kS/s.

Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications

Due to transistor leakage, CMOS circuits have a well-defined lower limit on their achievable energy efficiency [1]. Once this limit is reached, power-constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternate switching device with steeper sub-threshold slope—i.e., lower VDD/Ion for the same Ion/Ioff [2]. One promising class of such devices with nearly ideal Ion/Ioff characteristics are electro-statically actuated micro-electro-mechanical (MEM) switches [6]. Although mechanical movement makes MEM circuit delay significantly larger than that of CMOS, we have recently shown that with optimized circuit topologies MEM switches may potentially enable ∼10x lower energy over CMOS at up to ∼100MHz frequencies [3].

Energy-Aware Design of Compressed Sensing Systems for Wireless Sensors Under Performance and Reliability Constraints

This paper describes the system design of a compressed sensing (CS) based source encoding system for data compression in wireless sensor applications. We examine the trade-off between the required transmission energy (compression performance) and desired recovered signal quality in the presence of practical non-idealities such as quantization noise, input signal noise and channel errors. The end-to-end system evaluation framework was designed to analyze CS performance under practical sensor settings. The evaluation shows that CS compression can enable over 10X in transmission energy savings while preserving the recovered signal quality to roughly 8 bits of precision. We further present low complexity error control schemes tailored to CS that further reduce the energy costs by 4X as well as diversity scheme to protect against burst errors. Results on a real electrocardiography (EKG) signal demonstrate 10X in energy reduction and corroborate the system analysis.

Impact of incomplete set programing on the performance of phase change memory cell

Phase change memory (PCM) cells with T-shaped structure using tungsten heater were fabricated and the cell characteristics concerning the programing pulse width were also investigated in this work. The numerical modeling shows the thermal nonuniformity over the active region due to the considerable thermal sink of tungsten heater results in the amorphous-phase residues and the incomplete set programing. The experimental results reveal the existence of residual amorphous phase and indicate that the incomplete set programing is the dominant factor to degrade the PCM cell performances, such as the sensing margin and the endurance. The strategies to eliminate the incomplete set programing are the optimization in programing pulse width and the replacement of the tungsten heater with higher resistivity metal such as TiAlN.

Design and demonstration of micro-electro-mechanical relay multipliers

This paper describes the micro-architecture and circuit techniques for building multipliers with micro-electromechanical (MEM) relays. By optimizing the circuits and micro-architecture to suit relay device characteristics, the performance of the relay based multiplier is improved by a factor of ∼8× over any known static CMOS-style implementation, and ∼4× over CMOS pass-gate equivalent implementations. A 16-bit relay multiplier is shown to offer ∼10× lower energy per operation at sub-10 MOPS throughputs when compared to an optimized CMOS multiplier at an equivalent 90 nm technology node. To demonstrate the viability of this technology, we experimentally demonstrate the operation of the primary multiplier building block: a full (7:3) compressor, built with 98 MEM-relays, which is the largest working MEM-relay circuit reported to date.

Analysis and demonstration of MEM-relay power gating

This paper shows that due to their negligibly low leakage, in certain applications, chips utilizing power gates built even with todays relatively large, high-voltage micro-electro-mechanical (MEM) relays can achieve lower total energy than those built with CMOS transistors. A simple analysis provides design guidelines for off-time and savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. Finally, we demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based timer suitable for self-timed operation.

Enhanced Thermal Efficiency in Phase-Change Memory Cell by Double GST Thermally Confined Structure

A novel phase-change memory cell with a double- confinement structure was proposed and fabricated in this work. By having an additional bottom Ge2Sb2Te5 layer under the electrically confined active region, the heat loss can be effectively prevented. The temperature uniformity over the active region significantly improves and so does the thermal efficiency. Therefore, a low IRESET of about 0.3 mA and a reset power can be achieved. For the SET performance, a pulsewidth as low as 200 ns can be used without compromising the RSET.