Fred F. Chen

Common-mode backchannel signaling system for differential high-speed links

Common-mode signaling is effectively used to create a backchannel communication path over the existing pair of wires for a self-contained adaptive differential high-speed link transceiver cell. A transceiver chip was designed in 0.13 /spl mu/m CMOS to demonstrate the feasibility of simultaneous differential and common-mode signaling. The design uses a three-level return-to-null signaling scheme with simultaneous voltage and timing reference extraction, to minimize the hardware costs and achieve robust operation for sending update information from receiver to the transmitter. The measured results indicate that this backchannel achieves reliable communication without noticeable impact on the forward link for bandwidths up to 50MHz and swings of 20-100mV.

Relays do not leak: CMOS does

This paper describes the micro-architectural and circuit design techniques for building complex VLSI circuits with microelectromechanical (MEM) relays and presents experimental results to demonstrate the viability of this technology. By tailoring the circuits and micro-architecture to the relay device characteristics, the performance of the relay-based multiplier is improved by an order of magnitude over any known static CMOS style implementation, and by ~4x over CMOS pass-gate equivalent implementations. A 16-bit relay multiplier is shown to offer -10x lower energy per operation at sub-10 MOPS throughputs when compared to an optimized CMOS multiplier at an equivalent 90 nm technology node. The functionality of the primary multiplier building block, a full (7:3) compressor built with 46 scaled MEM-relays, which is the largest working MEM-relay circuit reported to date, is also demonstrated.

A 1-10 Gbps PAM2, PAM4, PAM2 partial response receiver analog front end with dynamic sampler swapping capability for backplane serial communications

A 1-10 Gbps receiver analog front end in 0.13 /spl mu/m CMOS enables a SERDES cell for backplane serial communications using differential PAM2, PAM4, or PAM2 partial response signaling with adaptive equalization. Dynamic sampler swapping and various built-in diagnostic capabilities enable receiver calibration and self-characterization with accuracy of < 0.4% UI in timing and < 2mV in voltage while receiving live data. Self-characterization results motivate modifications enabling communications at a BER of 10/sup -15/ with receiver sensitivity of +/-15mV.

Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system

High speed serial data transceivers often employ sophisticated communication techniques to balance out the effects of material loss and reflections. Link control hardware is required to initialize and adapt the link in a variety of signaling environments, often using loops with time constants which are orders of magnitude larger than the data unit interval (UI). This presents a big problem for the link modeling and verification, especially when link is a part of a larger digital system. We describe here the modeling and simulation method that overcomes this problem. The method is based on a standard hardware description language (HDL) and is applied to a fully adaptive, multi-mode, high-speed serial link system in a 36-channel switch fabric ASIC, designed in 0.13/spl mu/m CMOS process.