Carl W. Werner

Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver

To achieve high bit rates link designers are using more sophisticated communication techniques, often turning to 4PAM transmission or decision-feedback equalization (DFE). Interestingly, with only minor modification the same hardware needed to implement a 4PAM system can be used to implement a loop-unrolled single-tap DFE receiver. To get the maximum performance from either technique, the link has to be tuned to match the specific channel it is driving. Adaptive equalization using data based update filtering allows continuous updates while minimizing the required sampler front-end hardware and significantly reduces the cost of implementation in multi-level signaling schemes. A transceiver chip was designed and fabricated in 0.13 /spl mu/m CMOS process to investigate dual-mode operation and the modifications of the standard adaptive algorithms necessary to operate in high-speed link environments.

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

A 7.5Gb/s receiver has a 3-level DFE architecture to satisfy feedback timing requirements for 10 post-cursor taps. The receiver includes a second-order CDR with partial-response transition data filtering as well as a spectrally gated adaptation engine to prevent equalization updates during poor data patterns. The receiver consumes 136mW in a 90nm CMOS process

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

A 1.6 Gb/s/pin 4-PAM multi-drop signaling system has been implemented in 0.35-/spl mu/m CMOS. The system uses current-mode single-ended signaling, with three DC references shared across six I/O pins. A high-gain windowed integrating receiver with wide common-mode range was designed in order to improve SNR when operating with the smaller input overdrive of 4-PAM. Voltage and timing margins are measured via shmoos in a two-drop bussed system.

Common-mode backchannel signaling system for differential high-speed links

Common-mode signaling is effectively used to create a backchannel communication path over the existing pair of wires for a self-contained adaptive differential high-speed link transceiver cell. A transceiver chip was designed in 0.13 /spl mu/m CMOS to demonstrate the feasibility of simultaneous differential and common-mode signaling. The design uses a three-level return-to-null signaling scheme with simultaneous voltage and timing reference extraction, to minimize the hardware costs and achieve robust operation for sending update information from receiver to the transmitter. The measured results indicate that this backchannel achieves reliable communication without noticeable impact on the forward link for bandwidths up to 50MHz and swings of 20-100mV.

Characterizing sampling aperture of clocked comparators

Practical simulation and measurement methods based on impulse sensitivity functions to characterize the sampling aperture of clocked comparators are demonstrated on a 90 nm CMOS testchip. The results comparing a StrongARM latch and a CML latch suggest that the StrongARM latch has a narrower aperture of 23 ps but its aperture center is more sensitive to supply (65 ps/V). The CML latch has a higher sampling gain of 88.8 dB but a lower bandwidth of 6.8 GHz.

PLL On-Chip Jitter Measurement: Analysis and Design

Analysis of on-chip jitter measurements based on the dead-zone method reveals potentially large errors in the jitter variance estimate, when the jitter distribution is changing or not known a priori. To overcome this, a more accurate variance estimation method is proposed and experimentally verified. The residual error, caused by the correlated noise between the PLL and the measurement circuit, is fully characterized and circuit topologies are proposed to mitigate this type of error

A 1-10 Gbps PAM2, PAM4, PAM2 partial response receiver analog front end with dynamic sampler swapping capability for backplane serial communications

A 1-10 Gbps receiver analog front end in 0.13 /spl mu/m CMOS enables a SERDES cell for backplane serial communications using differential PAM2, PAM4, or PAM2 partial response signaling with adaptive equalization. Dynamic sampler swapping and various built-in diagnostic capabilities enable receiver calibration and self-characterization with accuracy of < 0.4% UI in timing and < 2mV in voltage while receiving live data. Self-characterization results motivate modifications enabling communications at a BER of 10/sup -15/ with receiver sensitivity of +/-15mV.

Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system

High speed serial data transceivers often employ sophisticated communication techniques to balance out the effects of material loss and reflections. Link control hardware is required to initialize and adapt the link in a variety of signaling environments, often using loops with time constants which are orders of magnitude larger than the data unit interval (UI). This presents a big problem for the link modeling and verification, especially when link is a part of a larger digital system. We describe here the modeling and simulation method that overcomes this problem. The method is based on a standard hardware description language (HDL) and is applied to a fully adaptive, multi-mode, high-speed serial link system in a 36-channel switch fabric ASIC, designed in 0.13/spl mu/m CMOS process.

Exploring Liquid Crystal Polymer (LCP) substrates for mm-Wave antennas in portable devices

There is a strong need for high efficiency antennas and passives for applications where high frequency operation, light weight, and conforming to a curved surface are required. In recent years there has been an increase in using flexible Liquid Crystal Polymer (LCP) substrates because of their inherent flexibility and improved loss characteristics. In particular there have been multiple efforts to use these substrates for microwave and mm-wave frequency ranges [1, 2].

A Multiband Transceiver System in 45-nm CMOS for Extended Data Rate through Notchy Wireline Channels

Various forms of discontinuities such as stubs, vias, and wire bonds can result in deep amplitude notches in wireline channels. The data rate for systems operating using such channels, in the absence of a power-hungry decision-feedback equalizer (DFE), is limited by the lowest notch frequency of the channel. This brief proposes a multiband transceiver system to overcome this limitation by upconverting part of the data using an on-off keying modulation to avoid operating near the notch frequency and multiplexes it with the original baseband data. The transceiver system implemented in 45-nm low-power CMOS and shows a 10%-50% increase in data rate with a power saving of 5%-30% over a traditional broadband system employing a DFE in exemplary channels.