Frederik Naessens

A unified instruction set programmable architecture for multi-standard advanced forward error correction

The continuously increasing number of communication standards to be supported in nomadic devices combined with the fast ramping design cost in deep submicron technologies claim for highly reusable and flexible programmable solutions. Software defined radio (SDR) aims at providing such solutions in radio baseband architectures. Great advances were recently booked in handset-targeted SDR, covering most of the baseband processing with satisfactory performance and energy efficiency. However, as it typically depicts a magnitude higher computation load, forward error correction (FEC) has been excluded from the scope of high throughput SDR solutions and let to dedicated hardware accelerators. The currently growing number of advanced FEC options claims however for flexibility there too. This paper presents the first application-specific instruction programmable architecture addressing in a unified way the emerging turbo- and LPDC coding requirements of 3GPP-LTE, IEEE802.11n, IEEE802.16(e) and DVB-S2/T2. The proposal shows a throughput from 0.07 to 1.25 Mbps/MHz with efficiencies round 0.32 nJ/bit/iter in turbo mode and round 0.085 nJ/bit/iter in LDPC mode. The area is lower than the cumulated area of dedicated turbo and LDPC solution.

A 10.37 mm2 675 mW reconfigurable LDPC and Turbo encoder and decoder for 802.11n, 802.16e and 3GPP-LTE

This paper describes the implementation of a flexible Turbo and LDPC outer modem engine which is capable of supporting the WiFi(802.11n), WiMax(802.16e) and 3GPPLTE standard on the same hardware resources. The chip is implemented in a 65nm CMOS technology and occupies 10.37 mm2. The decoder flexibility is offered by means of an application-specific instruction-set processor (ASIP), with full datapath reuse between Turbo and LDPC decoding. The encoders are dedicated ASIC datapaths. The maximum clock speed can be set to 320 MHz allowing a decoder output rate for a single iteration in excess of 140 Mbps for Turbo and 640 Mbps for LDPC with a maximum power consumption of 675 mW. The architecture template has been extended to support other standards like the DVB-S2/T2 LDPC decoding as well.

Impact of frequency offsets and IQ imbalance on MC-CDMA reception based on channel tracking

New air interfaces are currently being developed to meet the high spectral efficiency requirements of the emerging wireless communication systems. Multicarrier code-division multiple access (MC-CDMA) is seen as a promising candidate for the fourth-generation (4G) cellular communication systems because it can interestingly deal with the multipath propagation at a low processing complexity. Besides spectral efficiency and power consumption, the production cost of the transceiver should also be optimized. Direct conversion radio frequency (RF) receivers are appealing because they avoid costly intermediate frequency (IF) filters. However, they imply RF IQ separation, introducing a phase and amplitude mismatch between the I and Q branches. A communication system based on MC-CDMA is sensitive to synchronization errors and front-end non-idealities because it uses a long symbol duration. The goal of this paper is to evaluate the impact of the carrier frequency offset, the sampling clock offset, and the IQ imbalance on the MC-CDMA downlink system performance, considering a receiver based on channel tracking designed to cope with high mobility conditions. It is demonstrated that part of the effects is compensated by the channel estimation and an expression of the variance of the remaining symbol estimation error is provided. For the cellular system and the target performance considered in this paper, specifications are defined on the non-idealities. The results are validated with bit-error rate simulations

An integrated reconfigurable engine for multi-purpose sensing up to 6 GHz

We demonstrate a reconfigurable engine for multipurpose spectrum sensing within the cost and power constraints of mobile devices. The analog part builds up on the Scaldio reconfigurable analog front-end [1]. The digital part is an innovative Digital Front-end for Sensing capable of performing a range of sensing algorithms [3], which has now been fully implemented as a chip. The goal of this demo is the first demonstration of the digital chip, integrated with an analog front-end, enabling real-time validation of the sensing engine. The setup is validated for DVB-T and LTE, two important candidates for future DySPAN networks, as well as for very fast spectrum sweeping. This is the first integrated low power solution that can achieve such a very fast spectrum sweeping, thanks to the integration of two innovative components.

An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders

When combined with advanced FEC techniques such as the turbo code and LDPC code, soft-output MIMO sphere decoders significantly outperform hard-output sphere decoders. Hence, algorithms and implementations of soft-output sphere decoders have attracted intensive interest in recent years. Practical soft-output sphere decoder implementations often consist of a list generator and a LLR generator. Most existing implementations focus on the list generator, and the LLR generator is implemented in a relatively straightforward way. However, the LLR generator accounts for a great part of the complexity. Our contribution is an implementation friendly low complexity multiplierless LLR generator. We apply selective and incremental updating, algebraic simplifications and strength reductions to reduce the algorithmic complexity and to eliminate all multiplications. When integrated with the SSFE list generator, our scheme not only remove 100% multiplications, but also remove 26% to 83% additions, 76% to 94% bit-shifts and 63% to 91% memory operations. Besides the algorithmic aspects, we extract the key data-flow block with well-defined control signals. This can be easily mapped onto micro-architectures and implemented as the data-path in ASICs, or a function unit in ASIPs.

An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard

Multi-gigabit LDPC decoders are demanded by standards such as IEEE 802.11ad and IEEE 802.15.3c. In order to achieve high throughput, most published multi-gigabit designs use row-paralleled architecture. In this paper, we proposed a half-row paralleled LDPC decoder with half layer level pipeline and single permutation network for the 802.11ad standard, which reduces the hardware resources almost by half compared to the state-of-the-art row-paralleled LDPC decoder, achieving a good trade-off between energy efficiency and area efficiency. The decoder achieves a throughput of 5.6 Gbps and consumes only 99 mW for the highest coding rate 13/16 at 5 iterations, working at 500 MHz by using 40nm G technology, yielding an energy efficiency of 3.53 pJ/bit/iteration and area efficiency of 35 Gbps/sqmm.

Versatile Spectrum Sensing on Mobile Devices

Spectrum sensing is a key aspect in the realization of opportunistic radios, which will allow a significantly more efficient usage of the scarce spectrum resources. This paper presents a solution to upgrade mobile devices with spectrum sensing capabilities. A versatile digital component is proposed to meet a wide variety of use cases, at low cost and low power overhead. Complementary reconfigurable analog front-ends make the radio ready for upgrading wireless connectivity thanks to availability of information on spectrum occupancy.

A flexible ASIP decoder for combined binary and non-binary LDPC codes

This paper describes the implementation of a flexible combined binary and non-binary LDPC decoder. The ASIP architecture can be configured allowing re-use between both modes. Key in the architecture is parallelization, which is exploited in the SIMD engine. Binary LDPC codes intrinsically enables parallelization through layered decoding while in the non-binary case different trade-offs can be made. The implementation choice was made base on minimal memory requirement and computational effort. For a combination of supporting binary LDPC present within WLAN and WiMAX standard with non-binary GF(8) LDPC codes, a total area of 5.4 sqmm in commercial 65nm technology would be required. This size can be reduced towards 3.4 sqmm if only half of the non-binary decoding throughput is required.

A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication

The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of the transformation towards 4G. In this paper, we describe an energy efficient multi-Gbps LDPC decoder engine based on ASIP using Target tool suite. The ASIP core can be configured as half-layer paralleled or quarter-layer paralleled decoding, which offers a good trade-off between the throughput and power/area efficiency when compared to the state-of-art fully paralleled ASIC based multi-Gbps LDPC decoder. When the ASIP core is instantiated for 802.11ad, it achieved a throughput up to 5.3 Gbps at 5 iterations with a latency of less than 150 ns and a record energy efficiency of 4.3 pJ/bit/iteration in 40G TSMC technology for the coding rate 13/16, showing to be competitive versus published ASIC solutions.

Versatile sensing for mobile devices: cost, performance and hardware prototypes

Spectrum sensing received a lot of attention as a key aspect in the realization of opportunistic radios. Even today, there is a strong belief in the community that the cost and performance of sensing solutions dont meet the stringent requirements of Opportunistic Spectrum Access (OSA). In this paper, the cost and measured performance of a sensing solution is studied. The solution is versatile, and performance/cost analysis is performed for sensing of Digital Broadcast TV for OSA in the TV White Spaces and for sensing of LTE signals for improved coexistence with and for LTE networks. We show how the solution could be used to upgrade mobile devices with sensing capabilities, or as a standalone spectrum sensing prototype.