Lieven Hollevoet

A scalable 8.7nJ/bit 75.6Mb/s parallel concatenated convolutional (turbo-) CODEC

A 6 to 75.6Mb/s turbo CODEC with block size from 32 to 432, code rate from 1/3 to 3/4, 5.35/spl mu/s/block decoding latency and up to 8.25dB coding gain is described. This IC is fabricated in a 0.18/spl mu/m process and has a core area of 7.16mm/sup 2/. Energy-optimized architecture reduces the energy per bit to 8.7nJ and is almost constant over the throughput range.

A unified instruction set programmable architecture for multi-standard advanced forward error correction

The continuously increasing number of communication standards to be supported in nomadic devices combined with the fast ramping design cost in deep submicron technologies claim for highly reusable and flexible programmable solutions. Software defined radio (SDR) aims at providing such solutions in radio baseband architectures. Great advances were recently booked in handset-targeted SDR, covering most of the baseband processing with satisfactory performance and energy efficiency. However, as it typically depicts a magnitude higher computation load, forward error correction (FEC) has been excluded from the scope of high throughput SDR solutions and let to dedicated hardware accelerators. The currently growing number of advanced FEC options claims however for flexibility there too. This paper presents the first application-specific instruction programmable architecture addressing in a unified way the emerging turbo- and LPDC coding requirements of 3GPP-LTE, IEEE802.11n, IEEE802.16(e) and DVB-S2/T2. The proposal shows a throughput from 0.07 to 1.25 Mbps/MHz with efficiencies round 0.32 nJ/bit/iter in turbo mode and round 0.085 nJ/bit/iter in LDPC mode. The area is lower than the cumulated area of dedicated turbo and LDPC solution.

A 10.37 mm2 675 mW reconfigurable LDPC and Turbo encoder and decoder for 802.11n, 802.16e and 3GPP-LTE

This paper describes the implementation of a flexible Turbo and LDPC outer modem engine which is capable of supporting the WiFi(802.11n), WiMax(802.16e) and 3GPPLTE standard on the same hardware resources. The chip is implemented in a 65nm CMOS technology and occupies 10.37 mm2. The decoder flexibility is offered by means of an application-specific instruction-set processor (ASIP), with full datapath reuse between Turbo and LDPC decoding. The encoders are dedicated ASIC datapaths. The maximum clock speed can be set to 320 MHz allowing a decoder output rate for a single iteration in excess of 140 Mbps for Turbo and 640 Mbps for LDPC with a maximum power consumption of 675 mW. The architecture template has been extended to support other standards like the DVB-S2/T2 LDPC decoding as well.

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy

Energy scalable architectures and circuits for SDRs are proposed, for both a reconfigurable RF front-end and a heterogeneous multiprocessor SoC in a baseband platform. A performance/energy manager dynamically exploits the energy scalability and the dynamics in application requirements and propagation environment, realizing low-power operation. For the transmitter, the energy-scalability is translated to an average system-level energy-efficiency improvement of up to 40%.

An integrated reconfigurable engine for multi-purpose sensing up to 6 GHz

We demonstrate a reconfigurable engine for multipurpose spectrum sensing within the cost and power constraints of mobile devices. The analog part builds up on the Scaldio reconfigurable analog front-end [1]. The digital part is an innovative Digital Front-end for Sensing capable of performing a range of sensing algorithms [3], which has now been fully implemented as a chip. The goal of this demo is the first demonstration of the digital chip, integrated with an analog front-end, enabling real-time validation of the sensing engine. The setup is validated for DVB-T and LTE, two important candidates for future DySPAN networks, as well as for very fast spectrum sweeping. This is the first integrated low power solution that can achieve such a very fast spectrum sweeping, thanks to the integration of two innovative components.

Versatile Spectrum Sensing on Mobile Devices

Spectrum sensing is a key aspect in the realization of opportunistic radios, which will allow a significantly more efficient usage of the scarce spectrum resources. This paper presents a solution to upgrade mobile devices with spectrum sensing capabilities. A versatile digital component is proposed to meet a wide variety of use cases, at low cost and low power overhead. Complementary reconfigurable analog front-ends make the radio ready for upgrading wireless connectivity thanks to availability of information on spectrum occupancy.

A Scalable Baseband Platform for Energy-Efficient Reactive Software-Defined-Radio

The spectrum data-mining and agile air interface requirements of cognitive radios claim for software-defined-radio (SDR) implementations. The need to detect and/or generate virtually any kind of waveform in any band pushes the specification of such SDR to the limit. This makes cost-effective and energy-efficient implementation very challenging. As a first step toward effective embedded cognitive radio, we present the design, based on a top-down methodology, of a scalable SDR platform that enables spectrum environment awareness and reactive transmission. Hardware cost and energy-efficiency are contended by opportunistic partitioning and aggressive power management leading to 10 mW-range standby power and 100 mW-range active power

Nex generation digital front-end for multi-standard concurrent reception

This article presents an architecture of a Digital Front-End Receiver (DFE-Rx) for the next-generation mobile terminals. A main focus is placed in flexibility, scalability and concurrency. The architecture is capable of detecting, synchronizing and reporting carrier-frequency offset, of multiple concurrent radio standards. The proposed receiver is fabricated in a 65 nm CMOS low power high-VT cell technology in a die size of 5mm2. The synchronization engine has been measured at 1.2V and reports an average power consumption of 1.9mW during IEEE 802.11 (WLAN) reception and 1.6mW during configuration, while running at 10 MHz.

A 22 mW Multi-Standard Reconfigurable Spectrum Sensing Enabled Digital Frontend

Cognitive Radio requires the architecture of radio systems to combine reception and spectrum monitoring functionality efficiently. We propose a flexible digital front end that supports concurrent synchronization and sensing of high-throughput wireless standards. The chip is implemented in 65 nm CMOS technology resulting in a chip area of 6.4 mm2. Fine grain clock gating allows synchronization at 4 mW and sensing at 7 mW power consumption. Experiments with the chip in combination with a reconfigurable analog front end show that a 1.7 GHz wide frequency band can be scanned based on energy detection in an exceptionally low time window of 10 ms while consuming 13 mW power. Feature detection of DVB-T signals is implemented and measured as well and achieves for a single autocorrelation step a performance target false alarm rate of 10% and detection probability of 90% at an input power level of -106 dBm while consuming 7 mW power.

Distributed spectrum sensing in a cognitive networking testbed

In this demonstration, we show how the IBBT w-iLab.t wireless testbed, combined with multiple spectrum sensing engines designed by imec, can be used for experimentally-supported design and evaluation of cognitive networking protocols. Functionalities include the advanced characterization of the behavior of a cognitive solution under test, and characterization of the wireless experimentation environment itself.