Fredrick W. Trafton

An analog front-end signal processor for a 64 Mb/s PRML hard-disk drive channel

Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for high areal density on a hard-disk drive (HDD). Previously-published PRML channels include a 56 Mb/s channel design but without an on-chip programmable filter, synthesizer or servo demodulator. This 5V BiCMOS integrated circuit contains all the analog front-end functions necessary for a 64Mb/s HDD channel using a rate-8/9 code.<<ETX>>

An analog front-end signal processor for a 64 Mbits/s PRML hard-disk drive channel

This BiCMOS IC contains all the analog front-end components necessary for the design of a 21-64 Mb/s HDD channel. Major functional blocks include an automatic gain control circuit having both analog and digital modes of operation, a programmable filter with 6-33 MHz bandwidth range, two phase-locked loops with 24-72 MHz center frequency ranges, a differential 6 bit flash A/D converter with 24-72 MHz sampling rates, and a write precompensator having 600 ps step size. >

A method for overvoltage protection of a motor driver IC

This paper describes a circuit technique that allows semiconductor power devices to be safely used in an IC whose worst-case voltage requirements exceed the breakdown voltages of the power devices. The supply voltage is sensed and the circuit is placed into a non-operational but safe mode of operation (Turtle Mode/spl trade/). Device data is shown for a hard disk drive servo IC implementing this technique.