Fu-Chieh Hsu

Hot-electron-induced MOSFET degradation—Model, monitor, and improvement

Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si<inf>s</inf>H bonds. The device lifetime τ is proportional to<tex>I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5}</tex>. If I<inf>sub</inf>is large because of small<tex>L</tex>or large V<inf>d</inf>, etc., τ will be small. I<inf>sub</inf>(and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E<inf>m</inf>to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E<inf>m</inf>and I<inf>sub</inf>and, when properly designed, reduce device degradation.

Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement

Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with a physical model involving the breaking of the = Si/sub s/H bonds. The device lifetime /spl tau/ is proportional to...

Spatially resolved observation of visible-light emission from Si MOSFET's

Light emission from Si MOSFETs operating in the saturation region is observed. This observation provides direct evidence for the phenomenon of photocarrier generation in the substrate of VLSIs. The light emission appears to be uniform along the device width and emanates from the drain end of the MOSFET under normal operation. Light spots of much higher intensity are observed when the device is biased into the snap-back regime. This provides insights into the mechanism of snap-back breakdown.

A simplified model of short-channel MOSFET characteristics in the breakdown mode

When a short-channel MOSFET is driven into the avalanche-induced breakdown region, the drain current increases rapidly and usually shows a snapback characteristic. Both the substrate current and the current collected by a nearby reverse-biased p-n junction also increases with increasing drain current in this region of operation. All of these effects are associated with minority-carrier injection from the source junction into the substrate. A model for the drain I-V characteristics is proposed. Also presented is a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation. Experimental results agree well with the models.

Hot-electron induced excess carriers in MOSFET's

The existence of minority carriers in the substrate of n-channel MOSFETs operating in the saturation region is shown to be induced by turn-on of the source-substrate junction and photon generation. The two mechanisms are demonstrated experimentally and the photon-generation mechanism is further illustrated on a p-well CMOS wafer. Photon generation poses a constraint in VLSI dynamic RAM design.

Hot-electron substrate-current generation during switching transients

The characteristics of hot-electron substrate-current generation in n-channel MOSFETs during switching transients of an inverter are studied. The amount of substrate current generated depends strongly on the loading and the input transition time (switching speed) of the inverter. Most circuit elements including inverters, source followers, and transfer gates have similar behaviors in transient substrate-current generation. An analytical model is proposed to calculate the substrate-current generation with various supply voltages and input transition times. This model not only establishes the relationship between dc and transient substrate-current measurements, but also serves as a useful tool in predicting circuit/device reliability during actual circuit operations.

A simple punchthrough model for short-channel MOSFET's

Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometrical effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 1014and 6.6 × 1015cm-3and channel lengths from 1 to 2 µm show good agreement with the theory.

Correlating the channel, substrate, gate and minority-carrier currents in MOSFETs

An evaluation of measured linear and power-law relationships among the channel, substrate and minority-carrier currents, will be reported. The results simplify the visualizing, testing and modeling of hot-electron currents that affect IC performance and reliability.