Fule Li

A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO

This paper presents a low-power transceiver with a reconfigurable sliding-IF (intermediate frequency) architecture targeted for wireless body area networks hubs covering 400 MHz and 2.4 GHz bands. By using this architecture, a 1608-1988 MHz PLL synthesizer with only 21% tuning range can fully cover all the available bands around 400 MHz and 2.4 GHz as defined by IEEE 802.15.6 NB (narrow band) and ZigBee. The dual-band transceiver has been designed in 0.18 μm CMOS process. The design consists of a receiver with a wideband front-end and a reconfigurable amplifier-mixer, a transmitter with a reconfigurable two stage full quadrature mixer, a ΣΔ fractional-N PLL and some auxiliary circuits. The measurement result has demonstrated that the proposed transceiver can satisfy the dual-band requirements with comparable or even better performance in noise, receiver sensitivity and power consumption compared to previously-reported transceivers for only a single band.

A Low-Cost UHF RFID System With OCA Tag for Short-Range Communication

An ultrahigh-frequency RF identification system, consisting of a fully integrated tag and a special reader, has been developed for short-range and harsh size requirement applications. The system is fabricated in the standard 0.18-μm CMOS process. The whole tag chip with an antenna, an analog front end, a baseband, and memory takes up an area of 0.36 mm2, which is smaller than other reported tags with an on-chip antenna (OCA) using the standard CMOS process. A self-defined protocol is proposed to reduce the power consumption and minimize the size of the tag. A specialized system-on-a-chip reader system, consisting of RF transceiver, digital baseband, MCU, and host interface, supports both the self-defined and International Standards Organization 18000-6 C protocols. Its power consumption is about 500 mW, which is much lower than other reported readers considering the transmission power. Measurement results show that the systems reading range is 2 mm with a 20-dBm reader output power. In addition, it has been verified that the data stored in the OCA tag embedded in a pearl can be successfully read out. With an inductive antenna printed on a paper substrate around the OCA tag, the reading range can be extended from several centimeters to meters depending on the shape and size of the inductive antenna.

A RF remote-control transceiver with zero-standby power based on RFID technology

A zero standby power remote control system used for household appliances is presented in this paper. The system consists of two parts. One is transmitting unit and power amplifier which send RF modulated signal. The other is receiving unit and power management block which recover energy, demodulate the RF signal and control the power switch of the household appliances. Both transmit and receive ends only work during switching process so that the whole system has zero standby power consumption. The chip in transmitting unit is fabricated in 0.18um CMOS technology and occupies a core area of 0.47mm2. It works around 915MHz and has a max output power of OdBm. The total working power consumption of the chip is 16.45mW. The energy recovery block and ASK demodulation block in the receiving unit are verified.

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a high-speed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

An 85mW 14-bit 150MS/s pipelined ADC with 71.3dB peak SNDR in 130nm CMOS

A low-power 14-bit 150MS/s pipelined ADC is presented. This prototype ADC is fabricated in a 130nm CMOS process with a 1.3-V supply voltage. Range-scaling in the first stage enables a maximal 2Vp-p input signal swing with a power-efficient single-stage opamp. Opamp and capacitor sharing between the first and second stage reduces the opamp power consumption further. And the sample-and-hold amplifier (SHA)-less technique is also used to lower the power dissipation and noise. With digital calibration, the SNDR of the ADC is 71.3dB with a 2.4MHz input, and remains higher than 68dB for input frequencies up to 150MHz. The ADC consumes 85mW, which includes 57mW for the ADC core, 11mW for the low jitter clock receiver and 17mW for the high-speed reference buffer.

A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end

This paper presents a 12-bit 270MS/s pipelined analog-to-digital converter (ADC) without employing a front-end sample-and-hold amplifier. A novel strategy is established to diminish the aperture error while maintaining both the original tracking time and amplifying time of multiplying digital-to-analog converter (MDAC). It matches the signal paths between comparators and MDAC in the first stage by using proper timing sequence and high-speed dynamic comparators. The measurement results show 63.7dB SNR and 76.1dBc SFDR at 120.1MHz input frequency while the chips total power dissipation is 250mW (excluding LVDS drivers) at 1.2V supply. The ADC core occupies 1.7mm2 and is implemented in a 130nm CMOS process.

A low-power high-linearity symmetrical readout circuit for capacitive sensors

This paper presents a symmetrical readout circuit for capacitive sensors. Based on charge transfer principle, it is insensitive to stray capacitors. Introducing a reference branch, this symmetrical readout circuit can enlarge its linear range, reduce amplifier offsets and reject common-mode noise and even-order distortions. Chopper stabilization technique is used to reduce the negative effects of the amplifier offset and flicker (1/f) noise. A Verilog-A based varactor is used to model the real variable sensing capacitor. Simulation results are given for sensing capacitor changing frequency at 1 KHz. Metal-Insulator-Metal (MIM) capacitor array is designed on chip for measurement. Measurement results show that this circuit can achieve sensitivity of 370 mV/pF, linearity error below 1 % and power consumption as low as 2.5 mW. This symmetrical readout circuit can respond to FPGA controlled sensing capacitor array changed every 1 ms.

A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS

This paper presents a 5-50 Gb/s quarter-rate transmitter with a 4-tap feed-forward equalization (FFE) based on multiple-multiplexer (MUX). A bandwidth enhanced 4:1 MUX with the capability of eliminating charge-sharing effect is proposed to increase the maximum operating speed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming technique is designed. Implemented in 65 nm CMOS technology, the transmitter occupying an area of 0.6 mm2 achieves a maximum data rate of 50 Gb/s with an energy efficiency of 3.1 pJ/bit.

A low-power DC offset calibration method independent of IF gain for zero-IF receiver

A novel low-power DC offset calibration (DCOC) method independent of intermediate frequency (IF) gain for zero-IF receiver applications has been reported. The conventional analog DCOC method consumes greater power and affects the performance of the receiver. The conventional mixed-signal method requires enhanced memory to store the calibration results at different receiver gains as the DC offset is relative to the radio frequency (RF) and IF gain. A novel algorithm is presented to make the DCOC process independent of IF gain, which significantly reduces the memory area. With the proposed circuit, the receiver calibrates only once so settle-time and power consumption of the IF circuit is lowered. A DCOC circuit with the proposed method is manufactured in 0.18 μm CMOS technology that drains nearly 0 mA equivalent current from a 1.8 V power supply.摘要本文基于新型直流失调模型提出了一种应用于零中频接收机的新型直流失调校准方法。 该方法相比于传统的方法, 可以使校准过程独立于零中频接收机的中频增益, 大大简化了校准的复杂度, 有效地降低了校准电路所占用的芯片面积, 节约了芯片成本。 该方法只需要进行一次校准, 平均功耗接近为零, 远低于传统方法的功耗。 基于该方法, 我们实现了一种直流失调校准电路, 实际测试结果与仿真吻合, 很好地证明了该方法的创新性和实用性。

A 14-bit pipelined ADC with digital background nonlinearity calibration

A digital background calibration algorithm is proposed to overcome nonlinearity caused by finite opamp gain and capacitor mismatch in pipelined analog-to-digital converter (ADC). The scheme, code frequency statistics (CFS), does not modify the classic pipelined stage, needs none of extra testing signals, and reduces the linearity requirement of the analog circuit. CFS is suitable for generic input and the cost of hardware is low. An experimental 14-bit pipelined ADC is fabricated to verify CFS. At 15MS/s, the measurement results show that INL errors drop from 90LSB to 0.8 LSB, SNDR grows from 38.6 dB to 66.7 dB, THD drops from -37.3dB to -82.8dB, and SFDR grows from 41.6 dBc to 86.1 dBc. The linearity of the pipelined ADC is improved significantly.