Xuqiang Zheng

A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS

In this paper, a 10Gbps PI-based CDR circuit is presented in 65nm CMOS technology. The circuit is composed of a phase selector, a phase interpolator, a sample unit, a synchronize unit, a phase detector, and CDR logic. Half-rate clock is adopted to lessen the problems caused by high speed clocks and reduce power. The simulated worst phase step of phase interpolator is 26.7% larger than the average phase error. The power consumption is 15mW for 1V supply.

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a high-speed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology

This paper presents a 40 Gb/s (38.4-to-46.4 Gb/s) half rate SerDes transmitter with automatic serializing time window search and 2-tap pre-emphasis. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at the highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. A divider-less sub-harmonically injection-locked PLL (SILPLL) with auto-adjust injection timing is employed to provide low jitter clock source. A power-efficient 2-tap feed-forward equalizer (FFE) based on open loop 1-UI delay generation is implemented as the transmitter equalizer. Fabricated in 65 nm CMOS technology, the transmitter running at 40 Gb/s consumes 80 mW power under 1.2 V supply. The PLL RMS jitter is 98 fs integrating from 100 Hz to 100 MHz and the total jitter of 40 Gb/s eye diagram is 6.7 ps for 1e-12 BER.

A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS

This paper presents a 5-50 Gb/s quarter-rate transmitter with a 4-tap feed-forward equalization (FFE) based on multiple-multiplexer (MUX). A bandwidth enhanced 4:1 MUX with the capability of eliminating charge-sharing effect is proposed to increase the maximum operating speed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming technique is designed. Implemented in 65 nm CMOS technology, the transmitter occupying an area of 0.6 mm2 achieves a maximum data rate of 50 Gb/s with an energy efficiency of 3.1 pJ/bit.

A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

A 25 Gb/s transmitter (TX) and receiver (RX) chipset designed in a 65 nm CMOS technology is presented. The proposed quarter-rate TX architecture with divider-less clock generation can not only guarantee the timing constraint for the highest-speed serialization, but also save power compared with the conventional designs. A source-series terminated (SST) driver with a 2-tap feed-forward equalizer (FFE) and a far-end crosstalk canceller (XTC) is implemented in the TX chip. The RX chip employs an adaptive quarter-rate 2-tap decision-feedback equalizer (DFE) and a baud-rate clock and data recovery (CDR). The power-efficient DFE uses the combination of the soft-decision technique and a new dynamic structure. The DFE adaption logic and baud-rate CDR logic share a set of error samplers to save power and area. A hybrid alternate clock scheme is proposed to satisfy the timing requirement and reduce the power consumption further. The measurement results show that the TX and RX chipset totally compensates for a Nyquist channel loss of more than 40 dB, and consumes only 70 mW from a 1.2 V supply when operating at 25 Gb/s.

A 10Gb/s analog equalizer in 0.18um CMOS

This paper describes a 10Gb/s analog equalizer applied to transmitter. The equalizer consists of a continuous time linear equalizer (CTLE), with a shunt and double-series peaking network, which is used to enhance the bandwidth of the circuit and to boost the high frequency content of the signal. This paper deduces the circuits transfer function and proposes a design guidance to circuit design. The circuit is fabricated in 0.18um CMOS technology. The measurement results show that, when the chip delivers 10Gb/s PRBS7 data over a 6.3 inches FR4 channel, the output peak-to-peak jitter is 34ps. This circuit also works as a driver and has a good impendence matching. The power consumption of the equalizer is 30.2mW for 1.8V supply.

A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology

This paper presents a 50Gbps half rate SerDes transmitter with automatic serializing time window search. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. Fabricated in 65nm CMOS technology, the transmitter running at 50Gbps consumes only 75mW power under 1.2V power supply. The total jitter of 50Gbps eye diagram is 9.8ps for 1e-12 BER.

A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology

This paper describes the design of a low-jitter source-synchronous link transmitter macro for data rates of 9.6 Gb/s. The transmitter macro consists of 5 data channels plus 1 forwarded-clock channel. A low jitter PLL with bandwidth linearization is employed to achieve 0.66ps rms jitter. The power supply induced jitter is minimized by employing a hybrid clock distribution network which is proposed for both jitter and power consideration. To minimize the influence of PVT variation, Successive Approximation Register (SAR) sub block is implemented to accurately set the on chip impedance and the signal amplitude. A CML driver with 4 tap feed forward equalizer is implemented to compensate the channel loss. The transmitter is implemented in 65nm CMOS technology, the active chip area is 3.12 mm2.

A 76 mW 40-Gb/s SerDes transmitter with 64:1 MUX In 65-nm CMOS technology

This paper introduces a fully-integrated wireline transmitter operating at 40Gb/s. The transmitter incorporates a combiner of 64:1 MUX and 2-tap Feed-Forward-Equalizer (FFE). The transmitter is achieved in 65nm CMOS technology. The simulation results show that the proposed transmitter can work at 40Gb/s with a -11dB RLGC channel. The simulation power consumption is 76 mW under 1.08V supply, and the core area is 0.217 mm2.

A 15Gb/s wireline repeater in 65nm CMOS technology

This paper describes the design of a wireline repeater in 65nm CMOS technology. The T-coil networks with ESD protection are used in both repeaters input and output to realize impendence matching and bandwidth enhancement. Three continuous time linear equalizers (CTLE) placed in the data path are used to compensate for high frequencies loss, while the current mode logic (CML) buffer chain is used to compensate for DC loss. The measurement results show that the repeater could deliver 15 Gb/s data through a 10 inch channel which has a 19.2 dB loss at 7.5GHz. The power consumption is 2.67mW/Gbps under 1.1V supply voltage and the chip area is 0.63mm2.