Ziqiang Wang

A new globularity capsule endoscopy system with multi-camera

While wireless endoscopic capsule examining humans large gastrointestinal (GI) cavity, such as stomach and large intestine, it is possible that many interested spots are omitted by the one or two cameras due to its limited field of view. This paper proposes a new globularity capsule endoscopy system with multi-camera. Through analyzing the multi-camera systems optical characteristic and power consumption of the endoscopic capsule system, this paper proposes the spatial physical structure and the electronic architecture of the globularity capsule without blind area. Its diameter can be less than 15mm. The capsule can work in humans GI tract for 8 hours when the image frame rate is 4fps.

Ultra-low-voltage low-power charge pump for solar energy harvesting systems

This paper exploits a new charge pump used in integrated solar energy harvesting systems to improve the power efficiency under ultra low supply of under 0.7V supplied by on-chip photodiodes. Compared with conventional charge pumps, improvements of 20% in terms of output voltage gain and conversion efficiency can be achieved by using two symmetrical branches and PMOSFET-only transfer transistors per stage. The proposed circuit is implemented in UMC 0.18µm standard CMOS technology.

An asymmetric resonant coupling wireless power transmission link for Micro-Ball Endoscopy

This paper investigates the design and optimization of a wireless power transmission link targeting Micro-Ball Endoscopy applications. A novel asymmetric resonant coupling structure is proposed to deliver power to an endoscopic Micro-Ball system for image read-out after it is excreted. Such a technology enables many key medical applications with stringent requirements for small system volume and high power delivery efficiency. A prototyping power transmission sub-system of the Micro-Ball system was implemented. It consists of primary coil, middle resonant coil, and cube-like full-direction secondary receiving coils. Our experimental results proved that 200mW of power can be successfully delivered. Such a wireless power transmission capability could satisfy the requirements of the Micro-Ball based endoscopy application. The transmission efficiency is in the range of 41% (worst working condition) to 53% (best working condition). Comparing to conventional structures, Asymmetric Resonant Coupling Structure improves power efficiency by 13%.

A RF remote-control transceiver with zero-standby power based on RFID technology

A zero standby power remote control system used for household appliances is presented in this paper. The system consists of two parts. One is transmitting unit and power amplifier which send RF modulated signal. The other is receiving unit and power management block which recover energy, demodulate the RF signal and control the power switch of the household appliances. Both transmit and receive ends only work during switching process so that the whole system has zero standby power consumption. The chip in transmitting unit is fabricated in 0.18um CMOS technology and occupies a core area of 0.47mm2. It works around 915MHz and has a max output power of OdBm. The total working power consumption of the chip is 16.45mW. The energy recovery block and ASK demodulation block in the receiving unit are verified.

A low-cost, low-power UHF RFID reader transceiver for mobile applications

A low-cost, low-power UHF RFID reader transceiver for short-distance applications supporting ISO 18000-6C is presented in this paper, which is implemented in 0.18μm CMOS process. The reader transceiver is composed of a RF transceiver, a digital baseband, a MCU and host interface. In order to be used in consumer products, LDO modules are integrated so that the reader can works with lithium battery. Measured results show that the output power of the transmitter is 21dBm. With the proposed low noise transmitter and baseband low noise amplifier, the sensitivity of RX is -55dBm@-1dBm carrier leakage. The chip occupies 14mm2 and consumes 471mW from 3.3V power supply.

A new system design of the multi-view Micro-Ball endoscopy system

While the wireless endoscopic capsule examining humans large gastrointestinal (GI) cavity, such as stomach and large intestine, many interested spots are omitted by only one or two cameras due to its limited field of view. This paper proposes the new system architecture of the Micro-Ball for medical endoscopy application. Six cameras are embedded in the Micro-Ball for multiple fields of view, which can reduce endoscopic miss rate greatly. Based on this system architecture, a new working mode is proposed. The captured image data are saved in the Flash memory instead of being transmitted outside human body wirelessly. Only less than 6mJ is consumed when the Micro-Ball captures a frame of 480×480 image and writes the image data into the Flash memory. The endoscopic Micro-Ball can work in humans GI tract for 10 hours when the image frame rate is 2 fps. The Micro-Ball endoscopy system is verified on the FPGA-based demonstration system.

A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology

This paper presents a 40 Gb/s (38.4-to-46.4 Gb/s) half rate SerDes transmitter with automatic serializing time window search and 2-tap pre-emphasis. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at the highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. A divider-less sub-harmonically injection-locked PLL (SILPLL) with auto-adjust injection timing is employed to provide low jitter clock source. A power-efficient 2-tap feed-forward equalizer (FFE) based on open loop 1-UI delay generation is implemented as the transmitter equalizer. Fabricated in 65 nm CMOS technology, the transmitter running at 40 Gb/s consumes 80 mW power under 1.2 V supply. The PLL RMS jitter is 98 fs integrating from 100 Hz to 100 MHz and the total jitter of 40 Gb/s eye diagram is 6.7 ps for 1e-12 BER.

A novel demodulator for low modulation index RF signal in passive UHF RFID tag

This paper presents a novel ASK demodulator for passive UHF RFID (Radio Frequency Identification) tag, which can detect minimum 10% modulation index over a RF power range of 30dB. Compared with conventional nonlinear voltage and linear current demodulations, the detection sensitivity over a wider range is increased by adopting an innovative divisional linear voltage demodulation with ultra low power consumption. The demodulator is implemented in UMC 0.18µm mixed-mode CMOS technology. The power consumption is 3.95µW and it can be reduced to 3.08µW when the modulation index is large.

A fully integrated CMOS UHF RFID reader transceiver for handheld applications

This paper presents a fully integrated single-chip UHF radio frequency identification (RFID) reader transceiver for short distance handheld applications. The transceiver integrates an OOK modulator and a power amplifier in transmitter chain, an IQ direct-down converter, two operational amplifiers, and two comparators in the receiver chain. A PLL frequency synthesizer is also integrated on the same chip to provide the local oscillating signals for the transceiver. The measured output P1dB power of the transmitter is 16.4dBm and the measured receiver sensitivity is −60dBm. The on-chip integer-N synthesizer achieves a frequency resolution of 200kHz with a phase noise of −92.78 dBc/Hz at 100kHz frequency offset and −124.4 dBc/Hz at 1MHz frequency offset. The reader consumes a total power of 231.2mW when the output power is 16.4dBm. The proposed reader can communicate with commercial tags in a distance of more than 50cm without any off-chip power amplifier. The chip has a die area of 4.5mm⋆1.3mm including pads.

A combined low power SAR capacitance-to-digital / analog-to-digital converter for multisensory system

A low power interface circuit for multisensory system is presented in this paper. A SAR capacitance-to-digital converter (CDC) and a SAR analog-to-digital converter (ADC) are combined together so that capacitance or voltage from different sensors can be measured by the same circuit and converted to digital signal directly. A dynamic comparator with self-calibration is designed to achieve zero-static power. Bootstrapped switches and bottom-plate sampling are used to reduce the non-idealities of sample/hold circuit. The 11bit converter is designed in 0.18um CMOS process with a core area of 0.1764 mm2. It consumes 6.7μW and achieves an energy efficiency of 18.8 fJ/conversion-step as a CDC.