Fumihiro Koba

Tri-layer resist process for fabricating sub 45-nm L&S patterns by EPL

In this study, we have demonstrated a resist process to fabricate sub 45-nm lines and spaces (L&S) patterns (1:1) by using electron projection lithography (EPL) for a back-end-of-line (BEOL) process for 45-nm technology node. As a starting point we tried to fabricate sub 45-nm L&S (1:1) patterns using a conventional EPL single-layer resist process. There, the resolution of the EPL resist patterns turned out to be limited to 70 nm L&S (1:1) with aspect ratio (AR) of 3.3 which was caused by pattern collapse during the drying step in resist develop process. It has been common knowledge that pattern collapse of this type could be prevented by reducing the surface tension of the rinse-liquid and by decreasing the AR of the resist patterns. Therefore, we first applied a surfactant rinse to a single-layer resist process that could control the pattern collapse by its reduced surface tension. In this experiment, we used the ArF resist instead of the EPL resist because the surfactant that we were able to obtain was the one optimized to the ArF resist materials. From the results of ArF resist experiments, it was guessed that it was difficult for the EPL resist to obtain the L&S patterns with AR of 3.5 or more even if we used the surfactant optimized to the EPL resist. And we found that it was considerably difficult to form 45-nm L&S patterns with AR of 5.1 that was our target. Next, we evaluated a EPL tri-layer resist process to prevent pattern collapse by decreasing the AR of the resist patterns. Because in a tri-layer resist process the purpose of the top-layer resist is to transfer pattern to the middle-layer, a thinner top-layer resist was selected. By using the tri-layer resist process we were able to control the resist pattern collapse and thus were successful in achieving 40-nm L/S (1:1) top-layer resist patterns with AR of 2.3. The process also gave us 40-nm L&S (1:1) patterns after low-k film etching. And moreover, using our tri-layer resist process we were able to fabricate a wiring device with Cu/low-k. Although it was our first attempt, the process resulted in a high yield of 70 % for a 60-nm (1:1) wiring device. As a part of our study we conducted failure analysis of the results of our experiment. We found that the failures were located at the edge of the wafer and might originate in the bottom-layer pattern collapse. We thought that the wiring yield could be increased by control the bottom-layer pattern collapse. These findings indicated that our tri-layer resist process had a high applicability for device fabrication in BEOL.

Highly accurate proximity effect correction for 100 kV electron projection lithography

In this paper we provided an adequate approximation to an actual exposure intensity distribution (EID) for 100 kV electron projection lithography (EPL) by using a new function employing 2-Gaussian plus exponential model. We have evaluated correction accuracy of our new model using the optimum EID parameters. The parameters were extracted from measured resist linewidth exposed by using a mask with test patterns. The test patterns were resized by changing nominal EID parameters. We found that by using the new EID function with the optimum parameters the correction accuracy for pattern space dependency was improved by 8 nm. The EID function was especially effective to device patterns that had various line pitches. It was noteworthy that this simple EID function, consisting of only three terms, led to significant improvement in the correction accuracy.

Proximity effect correction using blur map in electron projection lithography

We demonstrate and evaluate proximity effect correction using blur map at a compromised focal plane in electron projection lithography. Critical dimension (CD) accuracy was improved from 12to5nm for 100nm L∕S pattern with 34% pattern area density by using blur maps calculated by space charge effect correction (SCEC) program, which is provided with the electron beam stepper NSR-EB1A by Nikon. CD error due to the SCEC was estimated to be 4nm, corresponding to 6nm in terms of blur for the resist process; this is substantiated by comparing the calculated and measured blurs that ranged from 6.3to−4.3nm.

Preliminary results of EB stepper in the application of 65-nm process

Electron projection lithography (EPL) is a promising candidate for next-generation lithography (NGL) at the 65 nm technology node and beyond. Nikon has developed the worlds first full-field EPL exposure tool, Nikons NSR-EB1A. This tool was shipped to Selete in June 2003. Final installation is still in progress, but we have begun evaluating its applicability to the 65 nm technology node through trial fabrication of a test element group (TEG). A TEG of via-hole chains consisting of 1st metal, 1st via, and 2nd metal layers was fabricated using optical/EPL mix-and-match lithography. We applied EPL to the via layer. The purpose of the first fabrication is to clarify practical hole resolution of the EPL tool because EPL is expected to define finer hole patterns and enable denser integration than optical lithography. To prevent defects in metal layers from adversely affecting evaluation, we used moderate pattern layouts in metal layers. Metal layers were defined by an ArF scanner to obtain good pattern fidelity and sufficient pattern yield. We used a single damascene process with a low-k insulator and Cu interconnection. Practical hole resolution was evaluated by electrical measurement and SEM and TEM observation. SEM confirmed that via holes of 70 nm were resolved. TEM confirmed that via-hole chains of 80 nm were fabricated. Electrical measurement confirmed electrical conduction through via-hole chains of 75 nm. These results suggest that applying EPL to hole layers could realize denser integration than optical lithography. EPL application to TEG trial fabrication demonstrates its high-resolution capability in practical use.

Contrast Evaluation of the SCALPEL GHOST in 100 kV Electron Projection Lithography.

We investigated the essential conditions for the SCALPEL GHOST for fabricating 80 nm devices in 100 kV electron projection lithography (EPL), in terms of the exposure intensity contrast. First, we estimated the energy backscattering coefficient, η, and the used resist contrast to be 0.76 and 23% by calculation and experiment at 50 kV. Then, using the obtained parameters and calculated exposure intensity contrast at 100 kV, we found that the SCALPEL GHOST will be applicable, with some resist improvements, when the beam blur of exposure systems, δ, is 45 nm or less.

Resolution improvement of EPL stencil mask using thin membrane

Electron Projection Lithography (EPL) provides a fundamental advantage in resolution. In this paper, resolution improvement of EPL masks and minimum resolution in EPL exposure are addressed. In order to improve the mask resolution, we applied membranes thinner than typical thickness of 2 um to e-beam scattering layers of the EPL stencil masks. Although strength of the membrane generally deteriorates with decrease in the membrane thickness, the EPL masks having 1-um-thick scattering layers were feasibly fabricated. Reduction of the membrane thickness down to 1 um considerably improved the mask minimum feature size to resolve 120-nm holes and 80-nm lines which corresponded to 30 nm and 20 nm on wafer dimension, respectively, in the 4x demagnification EPL exposure system. The application of the 1-um-thick membrane simultaneously brought the high resolution and good pattern qualities: CD uniformity less than 10 nm in 3σ with pattern sidewall angle range of 90° ± 0.2°. We performed wafer exposure experiments in combination of the EPL exposure tool NSR-EB1A (Nikon) and the 1-um-thick membrane mask, and obtained the resolution performance of 40-nm holes on the wafer. We conclude that the application of the 1-um-thick membrane to the e-beam CD qualities. The exposure resolution of 40-nm holes on the wafer reveals the EPL exposure system to be a potential solution for contact layers in the future technology node.

Application of Electron Projection Lithography to Via Formation in Two-Layer Metallization

In this paper we showed electron projection lithography (EPL) applicability to via formation in a back-end-of-line (BEOL) process for 45-nm technology node through fabricating a two-layer metallization device. We developed a single-layer via-resist process for 45-nm technology node. In order to prevent resist profile deteriorations, we optimized process conditions of a bottom anti-reflective coating (BARC) and an electrical conductive film (ECF). As a result, fine 60-nm (1:1) via-patterns were obtained after low-k dry-etching and 67-nm via-holes filling with Cu could be confirmed by using cross-sectional transmission electron microscope (TEM). These results suggested the single-layer via-resist process we developed could be applied for 45-nm technology node. In addition, for 32-nm technology node, we developed a tri-layer via-resist process that had a high resolution compared with a single-layer resist process. There, we could obtain extremely fine 40-nm (1:1) top-layer via-resist patterns. We believe that EPL has high applicability to via formation in BEOL process for not only 45-nm but also 32-nm technology node.

Performance and stability of electron projection lithography tool

The world’s first electron projection lithography (EPL) R&D exposure tool was installed at our laboratory in June 2003, and we have evaluated its basic performance. The most feasible introduction of EPL into ultra-large-scale integration (ULSI) is mix-and-match use with an optical tool for critical layers at the 65 nm technology node (TN) and beyond. Overlay is the most crucial issue in mix-and-match lithography, so we focused on overlay in this evaluation. We found that the overlay performance of the EPL tool in mix-and-match use is 48.0 nm in the X direction and 45.7nm in the Y direction. To clarify details of deteriorated overlay accuracy, we divided it into 7 factors, finding underlayer distortion to be about 15 nm, residual reticle distortion 5 nm, subfield (SF) distortion 15 nm, main-field (MF) distortion 20 nm, reticle alignment accuracy 15 nm, repeatability 25 nm, and exposure field distortion 25 nm. We also demonstrated that overlay accuracy was 30 nm using previous overlay data.

Design rule of hole-layer for electron projection lithography

Electron projection lithography (EPL) is a potential candidate for next-generation lithography (NGL) at the 65 nm technology node and beyond. EPL presents two key issues influencing design, because EPL uses EB and a stencil mask: beam blur and mask image placement (IP). Beam-blur deterioration depends on the Coulomb effect and is proportional to the beam current on the wafer, which depends on pattern density and the beam current on the mask. Pattern density in each subfield (SF) must be limited if the beam current on the mask is decided from throughput. IP accuracy of the stencil mask depends on the pattern layout. Intrinsic stress vanishes at openings, and distorted stress distribution causes IP error. To determine the influence of pattern layout on mask IP accuracy, simulation is checked in two steps. In the first step, simulation calculates the correlation between maximum displacement and pattern density in the entire SF. In the second step, simulation calculates the correlation between the side length of local area L and maximum additional displacement. The result of the first simulation shows that pattern deformation depends on the difference between half of the SF’s patterns density difference. To estimate the influence of pattern density imbalance in an area smaller than half of the SF, additional deformation of local area (L x L) is calculated in the second simulation step. Maximum additional displacement increases with L and pattern density. Based on the correlation between beam blur and pattern density and simulations results, the design rule (DR) for EPL is defined as the maximum pattern density in each entire SF and local area (L x L).

Contrast evaluation of SCALPEL GHOST method in 100 kV electron projection lithography

Electron projection lithography (EPL) techniques, such as SCALPEL and PREVAIL, are expected to be candidates for fabricating 80-nm devices or less. In electron-beam lithography, the proximity effect correction (PEC) is the most critical issue for obtaining sufficient dimension accuracy and good resist pattern profiles. The SCALPEL GHOST method, proposed by Watson et al. (1995), has a remarkable advantage to throughput by doing both the pattern and correction exposures, simultaneously. This method, however, degrades the exposure intensity contrast due to a larger background dose than that in other PEC methods, such as pattern modification. In this paper, we investigate the essential conditions for the SCALPEL GHOST PEC to achieve 80-nm resolution in 100 kV EFL in terms of the exposure intensity contrast.