Yoshihisa Matsubara

Application of Fluorinated Amorphous Carbon Thin Films for Low Dielectric Constant Interlayer Dielectrics

Fluorinated amorphous carbon thin films (a-C:F) for use as low-dielectric-constant interlayer dielectrics are deposited by helicon-wave plasma-enhanced chemical vapor deposition using fluorocarbon compounds as a source material. The a-C:F films can be grown from C4F8 at a high deposition rate (above 400 nm/min) and they are thermally stable up to 350°C. The addition of bias power to the substrate makes it possible to completely fill gaps in the wiring (space 0.35 µm, height 0.65 µm) with the a-C:F film. To protect the a-C:F film during further processing, a SiO2 film is deposited to add mechanical strength and resistance to the oxygen plasma used to remove resist materials. The adhesion between the a-C:F and SiO2 films is dramatically improved by inserting an adhesion promoter consisting of a-C:H and Si-rich SiO2. By using the a-C:F and SiO2 dielectrics and chemical mechanical polishing (CMP) process, globally planarized 3-level metallization is achieved. The a-C:F dielectric can reduce inter-line capacitance close to a half value as compared with the conventional SiO2 dielectrics.

Low-k fluorinated amorphous carbon interlayer technology for quarter micron devices

We have developed a new interlayer technology that attains a 50% reduction in capacitance and keeps good process compatibility with current Chemical Mechanical Polishing (CMP) based multi-level metallization (MLM) processes. This technology uses fluorinated amorphous carbon (a-C:F) with a dielectric constant of 2.3, sandwiched between layers of SiO/sub 2/, which are formed sequentially by high density plasma-chemical vapor deposition (HDP-CVD). The top SiO/sub 2/ layer assures oxygen plasma resistance during via etching, metal etching, and resist removal.

Activation energy for the C49‐to‐C54 phase transition of polycrystalline TiSi2 films with arsenic impurities

The C49‐to‐C54 transition in TiSi2 was investigated using samples having submicron line width film, by an x‐ray diffraction technique. Arrhenius plots of the transition rate show that the C49‐to‐C54 transition of polycrystalline TiSi2 films with arsenic impurities have an activation energy barrier strongly dependent on the arsenic concentration. The energy increases as a function of arsenic impurity concentration, from 3.5 eV for TiSi2 formed on Si substrate ion implanted with the dose of 2×1015 cm−2, to 7.8 eV with the dose of 5×1015 cm−2. The annealing time dependence of the x‐ray intensity on (004) orientation indicates that TiSi2 formed on Si substrate with the arsenic dose of 2×1015 cm−2 shows a diffusion‐limited process and that with the dose of 5×1015 cm−2 shows an interface‐limited process. The arsenic precipitates act to pin the C49 phase in the C49‐to‐C54 transition.

Deposition of silicon dioxide films on amorphous carbon films by plasma enhanced chemical vapor deposition for low dielectric constant interlayer dielectrics

Deposition of silicon dioxide films on fluorinated amorphous carbon films (a-C:F) for low dielectric constant interlayer dielectrics was investigated. Both SiO2 and a-C:F films were deposited by helicon wave plasma enhanced chemical vapor deposition with C4F8 for a-C:F and SiH4+O2 mixtures for SiO2. The SiO2 films on the a-C:F films peeled off soon after deposition. However, the peeling was suppressed by inserting a thin a-C:H buffer layer grown from CH4 between them. The adhesion between the films was increased by making the stoichiometry of SiO2 Si-rich. It was found that the Si–C bonds formed at the interface increased the adhesion.

Fluorinated Amorphous Carbon Thin Films Grown from C 4 F 8 for Multilevel Interconnections of Integrated Circuits

Fluorinated amorphous carbon thin films (a-C:F) for use as low-dielectric-constant (low-k) interlayer dielectrics were deposited by helicon-wave Plasma-Enhanced Chemical Vapor Deposition (PECVD) using fluorocarbon compounds as a source material. The a-C:F films could be grown from C 4 F 8 at a high deposition rate (above 400 nm/min) and they were thermally stable up to 300°C. The addition of bias power to the substrate made it possible to completely fill gaps in the wiring (space 0.35 μm, height 0.65 μm) with the a-C:F film. To protect the a-C:F film during further processing, we deposited an SiO 2 film to add mechanical strength and resistance to the oxygen plasma used to remove resist materials. The adhesion between the a-C:F and SiO 2 films was dramatically improved by inserting an adhesion promoter consisting of a-C:H and Si-rich SiO 2 .

Thermally robust 90 nm node Cu-Al wiring technology using solid phase reaction between Cu and Al

This paper describes a thermally robust and low cost Cu-Al wiring technology using solid phase reaction between ECD Cu and PVD Al. No significant sheet resistance and uniformity change has been obtained with precise Al concentration control. This technology dramatically improves reliable performance for stress induced voiding (SIV) as well as electro-migration (EM) and the most promising candidate for SIV free 90 nm Cu-Al process with lower cost.

A 0.18 /spl mu/m fully depleted CMOS on 30 nm thick SOI for sub-1.0 V operation

A process has been developed for fabricating 0.18 /spl mu/m CMOS devices that have excellent performance at low voltage. It uses fully depleted SOI technology. To suppress degradation of subthreshold slope due to the short channel effect, the SOI film is drastically thinned to 30 nm. An ultra-thin cobalt silicide layer efficiently reduces the high parasitic source/drain resistance that occurs with thin SOI film. The fabricated devices, which keep a subthreshold slope of less than 70 mV/decade, have a switching speed more than 1.5 times faster than that of bulk CMOS devices, when the supply voltage is 1.0 V or less.

Copper damascene using low dielectric constant fluorinated amorphous carbon interlayer

We have developed a new interconnect technique using a low-k (e t ,=2.5) organic interlayer (fluorinated amorphous carbon: a-C:F) and a low-resistivity metal line (copper). The new technique attains a duction in both the capacitance of the interlayer and the resistance of the metal line. We found that a-C:F on Cu reduces reflection to 10% for Kr-F line lithography. However, a-C:F cannot act as a protection layer for oxidation even at 200°C in atmospheric ambient annealing. Cu diffusion into a-C:F is about 100 nm at the annealing temperature of 450°C. The resistivity of the Cu line is 2.3–2.4 μΩ · cm for the 0.5-μm line width. Although the leakage current of the a-C:F ILD is one order higher than that of the SiO 2 ILD, electrical isolation is acceptable at

TiN-capped TiSi2 formation in W/TiSi2 process for a quarter-micron complementary metal-oxide-semiconductor

Abstract We have investigated the diffusion of nitrogen and oxygen into TiSi 2 through a thermally formed TiN capped layer. We have observed that nitrogen diffuses through the TiN capped layer into the TiSi 2 layer at temperatures above 200 °C, but oxygen diffuses into TiSi 2 through the TiN capped layer at temperatures above 400 °C. Both oxygen and nitrogen in the TiSi 2 film increase the C49-to-C54 phase transition temperature, and also degrade the morphology of selectively deposited tungsten films.

Tri-layer resist process for fabricating sub 45-nm L&S patterns by EPL

In this study, we have demonstrated a resist process to fabricate sub 45-nm lines and spaces (L&S) patterns (1:1) by using electron projection lithography (EPL) for a back-end-of-line (BEOL) process for 45-nm technology node. As a starting point we tried to fabricate sub 45-nm L&S (1:1) patterns using a conventional EPL single-layer resist process. There, the resolution of the EPL resist patterns turned out to be limited to 70 nm L&S (1:1) with aspect ratio (AR) of 3.3 which was caused by pattern collapse during the drying step in resist develop process. It has been common knowledge that pattern collapse of this type could be prevented by reducing the surface tension of the rinse-liquid and by decreasing the AR of the resist patterns. Therefore, we first applied a surfactant rinse to a single-layer resist process that could control the pattern collapse by its reduced surface tension. In this experiment, we used the ArF resist instead of the EPL resist because the surfactant that we were able to obtain was the one optimized to the ArF resist materials. From the results of ArF resist experiments, it was guessed that it was difficult for the EPL resist to obtain the L&S patterns with AR of 3.5 or more even if we used the surfactant optimized to the EPL resist. And we found that it was considerably difficult to form 45-nm L&S patterns with AR of 5.1 that was our target. Next, we evaluated a EPL tri-layer resist process to prevent pattern collapse by decreasing the AR of the resist patterns. Because in a tri-layer resist process the purpose of the top-layer resist is to transfer pattern to the middle-layer, a thinner top-layer resist was selected. By using the tri-layer resist process we were able to control the resist pattern collapse and thus were successful in achieving 40-nm L/S (1:1) top-layer resist patterns with AR of 2.3. The process also gave us 40-nm L&S (1:1) patterns after low-k film etching. And moreover, using our tri-layer resist process we were able to fabricate a wiring device with Cu/low-k. Although it was our first attempt, the process resulted in a high yield of 70 % for a 60-nm (1:1) wiring device. As a part of our study we conducted failure analysis of the results of our experiment. We found that the failures were located at the edge of the wafer and might originate in the bottom-layer pattern collapse. We thought that the wiring yield could be increased by control the bottom-layer pattern collapse. These findings indicated that our tri-layer resist process had a high applicability for device fabrication in BEOL.