Fumiko Yamashita

Demonstration of an N7 integrated fab process for metal oxide EUV photoresist

Inpria has developed a directly patternable metal oxide hard-mask as a robust, high-resolution photoresist for EUV lithography. In this paper we demonstrate the full integration of a baseline Inpria resist into an imec N7 BEOL block mask process module. We examine in detail both the lithography and etch patterning results. By leveraging the high differential etch resistance of metal oxide photoresists, we explore opportunities for process simplification and cost reduction. We review the imaging results from the imec N7 block mask patterns and its process windows as well as routes to maximize the process latitude, underlayer integration, etch transfer, cross sections, etch equipment integration from cross metal contamination standpoint and selective resist strip process. Finally, initial results from a higher sensitivity Inpria resist are also reported. A dose to size of 19 mJ/cm2 was achieved to print pillars as small as 21nm.

Direct etched Cu characterization for advanced interconnects

Cu wires patterning by direct etch methods is investigated at 300mm wafer level. Cross-sectional sidewall profiles with tapering angles around 74.5° are obtained with a mid-line width of 44 nm, which paves the way to further scaling of this technique. Lower resistivity is demonstrated with respect to conventional Cu damascene process, with low leakage current between adjacent Cu lines. An in-situ 10nm SiN cap is deposited as a passivation to enable electrical and reliability tests. The electromigration (EM) characterization shows promising reliability performance of the direct etched Cu wires.

Wafer edge overlay control solution for N7 and beyond

Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

Patterning with metal-oxide EUV photoresist: patterning capability, resist smoothing, trimming, and selective stripping

Inpria metal-oxide photoresist (PR) serves as a thin spin-on patternable hard mask for EUV lithography. Compared to traditional organic photoresists, the ultrathin metal-oxide photoresist (~12nm after development) effectively mitigates pattern collapse. Because of the high etch resistance of the metal-oxide resist, this may open up significant scope for more aggressive etches, new chemistries, and novel integration schemes. We have previously shown that metal-oxide PR can be successfully used to pattern the block layer for the imec 7-nm technology node[1] and advantageously replace a multiple patterning approach, which significantly reduces the process complexity and effectively decreases the cost. We also demonstrated the formation of 16nm half pitch 1:1 line/space with EUV single print[2], which corresponds to a metal 2 layer for the imec 7-nm technology node. In this paper, we investigate the feasibility of using Inpria’s metal-oxide PR for 16nm line/space patterning. In meanwhile, we also explore the different etch process for LWR smoothing, resist trimming and resist stripping.