Ming Mao

Towards manufacturing a 10nm node device with complementary EUV lithography

For device manufacturing at the 10nm node (N10) and below, EUV lithography is one of the technology options to achieve the required resolution. Besides high throughput and extreme resolution, excellent wafer CD, overlay and defect control are also required. In this paper, we discuss two wafer CD uniformity issues, the effect of the reticle black border and photon shot noise. The readiness of EUV lithography for N10 will be discussed by showing on-product imaging and overlay performance of a self aligned via layer inserted with EUV lithography. EUV single patterning results will be discussed by comparing the imaging performance of our NXE:3100 cluster to the NXE:3300 at ASML. Last but not least, the extendibility of EUV lithography towards sub 10nm patterning will be discussed by demonstrating sub 10nm half pitch LS patterns with EUV single Self Aligned Double Patterning (SADP).

Overlay metrology solutions in a triple patterning scheme

Overlay metrology tool suppliers are offering today several options to their customers: Different hardware (Image Based Overlay or Diffraction Based Overlay), different target designs (with or without segmentation) or different target sizes (from 5 um to 30 um). All these variations are proposed to resolve issues like robustness of the target towards process variations, be more representative of the design or increase the density of measurements. In the frame of the development of a triple patterning BEOL scheme of 10 nm node layer, we compare IBO targets (standard AIM, AIMid and multilayer AIMid). The metrology tools used for the study are KLA-Tencor’s nextgeneration Archer 500 system (scatterometry- and imaging-based measurement technologies on the same tool). The overlay response and fingerprint of these targets will be compared using a very dense sampling (up to 51 pts per field). The benefit of indie measurements compared to the traditional scribes is discussed. The contribution of process effects to overlay values are compared to the contribution of the performance of the target. Different targets are combined in one measurement set to benefit from their different strengths (performance vs size). The results are summarized and possible strategies for a triple patterning schemes are proposed.

Exploring the readiness of EUV photo materials for patterning advanced technology nodes

Imec is currently driving the extreme ultraviolet (EUV) photo material development within the imec material and equipment supplier hub. EUV baseline processes using the ASML NXE3300 full field scanner have been setup for the critical layers of the imec N7 (iN7) BEOL process modules with a resist sensitivity of 35mJ/cm2, 40mJ/cm2 and 60mJ/cm2 for metal, block and vias layer, respectively. A feasibility study on higher sensitivity resists for HVM has been recently conducted looking at 16nm dense line-space at a targeted exposure dose of 20mJ/cm2. Such a study reveals that photoresist formulations with a cost-effective resist sensitivity are feasible today. Moreover, recent advances in enhanced underlayers are further offering novel development opportunities to increase the resist sensitivity. However, line width roughness (LWR) and pattern defectivity at nano scale are the major limiting factors of the lithographic process window and further efforts are needed to reach a HVM maturity level. We will present the results of the photo material screening and we examine in detail the lithography patterning results for the best performing photoresists. We further discuss the fundamental aspects of photo materials from a light-matter interaction standpoint looking at the photo emission yield at the EUV light for different photo materials towards a better understanding of the relation between photon efficiency and patterning performance. Finally, as metal containing resists are becoming part of the EUV material landscape, we also review the manufacturing aspects of a such class of resists looking at metal cross contamination pattern and defectivity on the process equipment.

Demonstration of an N7 integrated fab process for metal oxide EUV photoresist

Inpria has developed a directly patternable metal oxide hard-mask as a robust, high-resolution photoresist for EUV lithography. In this paper we demonstrate the full integration of a baseline Inpria resist into an imec N7 BEOL block mask process module. We examine in detail both the lithography and etch patterning results. By leveraging the high differential etch resistance of metal oxide photoresists, we explore opportunities for process simplification and cost reduction. We review the imaging results from the imec N7 block mask patterns and its process windows as well as routes to maximize the process latitude, underlayer integration, etch transfer, cross sections, etch equipment integration from cross metal contamination standpoint and selective resist strip process. Finally, initial results from a higher sensitivity Inpria resist are also reported. A dose to size of 19 mJ/cm2 was achieved to print pillars as small as 21nm.

Influence of etch process on contact hole local critical dimension uniformity in extreme-ultraviolet lithography

Contact Hole (CH) Local Critical Dimension Uniformity (LCDU) has a direct impact on device performance. As a consequence, being able to understand and quantifying the different LCDU contributors and the way they evolve during the various process steps is critical. In this work the impact of etch process on LCDU for different resists and stacks is investigated on ASML NXE:3100 and NXE:3300. LCDU is decomposed into shot noise, mask, and metrology components. The design of the experiment is optimized to minimize the decomposition error. CD and LCDU are monitored and found to be stable. We observed that the net effect of the etch process is to improve LCDU, although the final LCDU is both stack- and resist-dependent. Different resists demonstrate the same LCDU improvement, so that the LCDU after etch will depend on the initial resist performance. Using a stack different from the one used to set up the etch process can undermine the LCDU improvement. The impact of the various etch steps is investigated in order to identify the physical mechanisms responsible for the LCDU improvement through etch. Both top-down and cross section Scanning Electron Microscopy (SEM) are used. The step-by-step analysis of the etch process showed that the main LCDU improvement is achieved during oxide etch, while the other process steps are either ineffective or detrimental in terms of LCDU. The main cause of the LCDU improvement is then attributed to the polymerization of the CH surface happening during the oxide etch. Finally, the LCDU improvement caused by the etch process is investigated as a function of the initial LCDU after litho in a relatively broad range (2-15nm). The ratio between LCDU after litho over LCDU after etch is investigated as a function of the initial LCDU after litho for two different resists. The results indicate that the impact of etch on LCDU is characterized by a single curve, specific to the etch process in use and independent of the resist type. In addition, we observe that the percentage LCDU improvement is constant above a certain threshold, in agreement with the throughpitch results.

Single exposure EUV patterning of BEOL metal layers on the IMEC iN7 platform

This paper summarizes findings on the iN7 platform (foundry N5 equivalent) for single exposure EUV (SE EUV) of M1 and M2 BEOL layers. Logic structures within these layers have been measured after litho and after etch, and variability was characterized both with conventional CD-SEM measurements as well as Hitachi contouring method. After analyzing the patterning of these layers, the impact of variability on potential interconnect reliability was studied by using MonteCarlo and process emulation simulations to determine if current litho/etch performance would meet success criteria for the given platform design rules.

SAQP and EUV block patterning of BEOL metal layers on IMEC's iN7 platform

The imec N7 (iN7) platform has been developed to evaluate EUV patterning of advanced logic BEOL layers. Its design is based on a 42 nm first-level metal (M1) pitch, and a 32 nm pitch for the subsequent M2 layer. With these pitches, the iN7 node is an ‘aggressive’ full-scaled N7, corresponding to IDM N7, or foundry N5. Even in a 1D design style, single exposure of the 16 nm half-pitch M2 layer is very challenging for EUV lithography, because of its tight tip-to-tip configurations. Therefore, the industry is considering the hybrid use of ArFi-based SAQP combined with EUV Block as an alternative to EUV single exposure. As a consequence, the EUV Block layer may be one of the first layers to adopt EUV lithography in HVM. In this paper, we report on the imec iN7 SAQP + Block litho performance and process integration, targeting the M2 patterning for a 7.5 track logic design. The Block layer is exposed on an ASML NXE:3300 EUV-scanner at imec, using optimized illumination conditions and state-of-the-art metal-containing negative tone resist (Inpria). Subsequently, the SAQP and block structures are characterized in a morphological study, assessing pattern fidelity and CD/EPE variability. The work is an experimental feasibility study of EUV insertion, for SAQP + Block M2 patterning on an industry-relevant N5 use-case.

Co-optimization of lithographic and patterning processes for improved EPE performance

Complimentary lithography is already being used for advanced logic patterns. The tight pitches for 1D Metal layers are expected to be created using spacer based multiple patterning ArF-i exposures and the more complex cut/block patterns are made using EUV exposures. At the same time, control requirements of CDU, pattern shift and pitch-walk are approaching sub-nanometer levels to meet edge placement error (EPE) requirements. Local variability, such as Line Edge Roughness (LER), Local CDU, and Local Placement Error (LPE), are dominant factors in the total Edge Placement error budget. In the lithography process, improving the imaging contrast when printing the core pattern has been shown to improve the local variability. In the etch process, it has been shown that the fusion of atomic level etching and deposition can also improve these local variations. Co-optimization of lithography and etch processing is expected to further improve the performance over individual optimizations alone. To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes. Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.

Single exposure EUV of 32nm pitch logic structures: patterning performance on BF and DF masks

This paper summarizes findings for an N5 equivalent M2 (pitch 32) layer patterned by means of SE EUV. Different mask tonalities and resist tonalities have been explored and a full patterning (litho plus etch) process into a BEOL stack has been developed. Resolution enhancement techniques like SRAFs insertion and retargeting have been evaluated and compared to a baseline clip just after OPC. Steps forward have been done to develop a full patterning process using SE EUV, being stochastics and variability the main items to address.

Electrical comparison of iN7 EUV hybrid and EUV single patterning BEOL metal layers

The semiconductor scaling roadmap shows the continuous node to node scaling to push Moore’s law down to the next generations. In that context, the foundry N5 node requires 32nm metal pitch interconnects for the advanced logic Back- End of Line (BEoL). 193immersion usage now requires self-aligned and/or multiple patterning technique combinations to enable such critical dimension. On the other hand, EUV insertion investigation shows that 32nm metal pitch is still a challenge but, related to process flow complexity, presents some clear motivations. Imec has already evaluated on test chip vehicles with different patterning approaches: 193i SAQP (Self-Aligned Quadruple Patterning), LE3 (triple patterning Litho Etch), tone inversion, EUV SE (Single Exposure) with SMO (Source-mask optimization). Following the run path in the technology development for EUV insertion, imec N7 platform (iN7, corresponding node to the foundry N5) is developed for those BEoL layers. In this paper, following technical motivation and development learning, a comparison between the iArF SAQP/EUV block hybrid integration scheme and a single patterning EUV flow is proposed. These two integration patterning options will be finally compared from current morphological and electrical criteria.