Fumio Iwamoto

EUV lithography program at IMEC

IMEC has started an EUV lithography research program based on ASMLs EUV full field scanner, the Alpha Demo Tool (ADT). Currently, the ADT is in the final phase of installation. The program focuses on three main projects: EUV resists, EUV reticles and assessment of the ADT performance. The intent of this program is to help improve and establish the necessary mask and resist infrastructure. In this paper, the status and the progress of the program is reviewed. In preparation for a resist process for the ADT, interference lithography has been used to track the progress of resist performance. Steady progress in resist development is seen, especially in terms of resolution, as some materials are now able to resolve 25nm HP. In its initial phase, the reticle project has concentrated on working with the mask and blank suppliers to assure timely availability of reticles for the ADT. An overview is given of the other reticle related activities, as well as first results of a defect printability study by simulation. In the ADT assessment project, simulation studies are reported aimed at the development of optical correction for flare and reticle shadowing effects. The impact of flare and shadowing effects are well understood and strategies for flare mitigation and shadowing effect correction are proposed.

Dependence of EUV Mask Printing Performance on Blank Architecture

EUV lithography is the leading candidate for sub-32nm half-pitch device manufacturing. This paper deals with the investigation of the impact of the mask blank architecture on the wafer print by EUV lithography. Presently the material stack on the mask is not fixed and different suppliers offer a range of variation. The purpose of the present paper is threefold, as detailed hereafter. First it is shown that there are possibilities to make EUV masks less prone to reflectivity loss by carbon contamination. An estimate is given for the required limitations on mask contamination and fabrication tolerance to keep the imaging impact below acceptable levels. These data can be used as preliminary error budgets for the individual and combined capping layer deterioration phenomena. Further-on, printing results on the Alpha Demo Tool (ADT) are reported, obtained with different reticles with identical layout produced on blanks with different mask stacks. In preparation for this experimental work simulations have been undertaken. The experimental results show good agreement in printing performance between the reticles tested. Finally, our work clearly shows the opportunity to reduce the absorber thickness without noticeable loss of contrast and with the big advantage of shadowing effect reduction.

Innovative metrology for wafer edge defectivity in immersion lithography

In semiconductor manufacturing, the control of defects at the edge of the wafer is a key factor to keep the number of yielding die on a wafer as high as possible. Using dry lithography, this control is typically done by an edge bead removal (EBR) process, which is understood well. Immersion lithography however changes this situation significantly. During this exposure, the wafer edge is locally in contact with water from the immersion hood, and particles can then be transported back and forth from the wafer edge area to the scanner wafer stage. Materiel in the EBR region can also potentially be damaged by the dynamic force of the immersion hood movement. In this paper, we have investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to the inspection of the flat top part of the wafer edge, due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution. This study utilized KLA-Tencors VisEdge, a new automated edge inspection system, that provides full wafer edge imaging (top, side, bottom) using laser-based optics and multi-sensor detection, and where defects of interest can be classified with Automated Defect Classification (ADC) software. Using the VisEdge technology, the impact from the immersion lithography towards wafer edge defectivity is investigated. The work revealed several key challenges to keep the wafer edge related defectivity under control : choice of resist, optimization of EBR recipes, scanner pollution and related memory effects, wafer handling, device processing, etc... Contributing to the understanding of the mechanisms of wafer edge related immersion defects and to the optimization the die yield level, this technology is believed to be important when the immersion processes are introduced in semiconductor manufacturing.