Bart Baudemprez

EUV lithography program at IMEC

IMEC has started an EUV lithography research program based on ASMLs EUV full field scanner, the Alpha Demo Tool (ADT). Currently, the ADT is in the final phase of installation. The program focuses on three main projects: EUV resists, EUV reticles and assessment of the ADT performance. The intent of this program is to help improve and establish the necessary mask and resist infrastructure. In this paper, the status and the progress of the program is reviewed. In preparation for a resist process for the ADT, interference lithography has been used to track the progress of resist performance. Steady progress in resist development is seen, especially in terms of resolution, as some materials are now able to resolve 25nm HP. In its initial phase, the reticle project has concentrated on working with the mask and blank suppliers to assure timely availability of reticles for the ADT. An overview is given of the other reticle related activities, as well as first results of a defect printability study by simulation. In the ADT assessment project, simulation studies are reported aimed at the development of optical correction for flare and reticle shadowing effects. The impact of flare and shadowing effects are well understood and strategies for flare mitigation and shadowing effect correction are proposed.

Imaging performance of the EUV alpha semo tool at IMEC

Extreme Ultraviolet Lithography (EUVL) is the leading candidate beyond 32nm half-pitch device manufacturing. Having completed the installation of the ASML EUV full-field scanner, IMEC has a fully-integrated 300mm EUVL process line. Our current focus is on satisfying the specifications to produce real devices in our facilities. This paper reports on the imaging fingerprint of the EUV Alpha Demo Tool (ADT), detailing resolution, imaging, and overlay performance. Particular emphasis is given to small pitch contact holes, which are a critical layer for advanced manufacturing nodes and one of the most likely layers where EUVL may take over from 193nm lithography. Imaging of contact holes, pattern transfer and successful printing of the contact hole level on a 32nm SRAM device is demonstrated. The impact of flare and shadowing on EUV ADT performance is characterized experimentally, enabling the implementation of appropriate mitigation strategies.

Demonstration of scaled 0.099µm 2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

We demonstrate electrically functional 0.099µm² 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with L<inf>g</inf>∼40nm, 12–17nm wide Fins, and cell β ratio ∼1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ≥30nm-wide contacts. SRAM cell with SNM≫10%V<inf>DD</inf> down to 0.4V, and healthy electrical characteristics for the cell transistors [SS∼80mV/dec, DIBL∼50–80mV/V, and |V<inf>Tlin</inf>|≤0.2V (PMOS), V<inf>Tlin</inf>∼0.36V (NMOS)] are reported.

Stability and imaging of the ASML EUV alpha demo tool

Extreme Ultra-Violet (EUV) lithography is the leading candidate for semiconductor manufacturing of the 22nm technology node and beyond, due to the very short wavelength of 13.5nm. However, reducing the wavelength adds complexity to the lithographic process. The impact of the EUV specific conditions on lithographic performance needs to be understood, before bringing EUV lithography into pre-production. To provide early learning on EUV, an EUV fullfield scanner, the Alpha Demo Tool (ADT) from ASML was installed at IMEC, using a Numerical Aperture (NA) of 0.25. In this paper we report on different aspects of the ADT: the imaging and overlay performance and both short and long-term stability. For 40nm dense Lines-Spaces (LS), the ADT shows an across field overlapping process window of 270nm Depth Of Focus (DOF) at 10% Exposure Latitude (EL) and a wafer CD Uniformity (CDU) of 3nm 3σ, without any corrections for process or reticle. The wafer CDU is correlated to different factors that are known to influence the CD fingerprint from traditional lithography: slit intensity uniformity, focus plane deviation and reticle CD error. Taking these contributions into account, the CD through slit fingerprint for 40nm LS is simulated with excellent agreement to experimental data. The ADT shows good CD stability over 9 months of operation, both intrafield and across wafer. The projection optics reflectivity has not degraded over 9 months. Measured overlay performance with respect to a dry tool shows |Mean|+3σ below 20nm with more correction potential by applying field-by-field corrections (|Mean|+3σ ≤10nm). For 22nm SRAM application, both contact hole and metal layer were printed in EUV with 10% CD and 15nm overlay control. Below 40nm, the ADT shows good wafer CDU for 30nm dense and isolated lines (on the same wafer) and 38nm dense Contact Holes (CH). First 28nm dense line CDU data are achieved. The results indicate that the ADT can be used effectively for EUV process development before installation of the pre-production tool, the ASML NXE Gen. 1 at IMEC.

Dependence of EUV Mask Printing Performance on Blank Architecture

EUV lithography is the leading candidate for sub-32nm half-pitch device manufacturing. This paper deals with the investigation of the impact of the mask blank architecture on the wafer print by EUV lithography. Presently the material stack on the mask is not fixed and different suppliers offer a range of variation. The purpose of the present paper is threefold, as detailed hereafter. First it is shown that there are possibilities to make EUV masks less prone to reflectivity loss by carbon contamination. An estimate is given for the required limitations on mask contamination and fabrication tolerance to keep the imaging impact below acceptable levels. These data can be used as preliminary error budgets for the individual and combined capping layer deterioration phenomena. Further-on, printing results on the Alpha Demo Tool (ADT) are reported, obtained with different reticles with identical layout produced on blanks with different mask stacks. In preparation for this experimental work simulations have been undertaken. The experimental results show good agreement in printing performance between the reticles tested. Finally, our work clearly shows the opportunity to reduce the absorber thickness without noticeable loss of contrast and with the big advantage of shadowing effect reduction.

In-line lithography cluster monitoring and control using integrated scatterometry

In the continuous drive for smaller feature sizes, process monitoring becomes increasingly important to compensate for the smaller lithography process window and to assure that Critical Dimensions (CD) remain within the required specifications. Moreover, the higher level of automation in manufacturing enables almost real-time correction of lithography cluster machine parameters, resulting in a more efficient and controlled use of the tools. Therefore, fast and precise in-line lithography metrology using Advanced Process Control (APC) rules are becoming crucial, in order to guarantee that critical dimensions stay correctly targeted. In this paper, the feasibility of improving the CD control of a 193nm lithography cluster has been investigated by using integrated scatterometry. The target of the work was to identify if a dose correction on field and wafer level, based on precise in-line measurements, could improve the overall CD control. Firstly, the integrated metrology has been evaluated extensively towards precision and sensitivity in order to prove its benefits for this kind of control. Having a long-term repeatability of significantly better than 0.75nm 3σ, this was very promising towards the requirements for sub-nanometer CD correction. Moreover, based on an extensive evaluation of the process window on the lithography cluster, it has been shown that the focus variation is minimal and that CD control can be improved using dose correction only. In addition, systematic variations in across-wafer uniformity and across-lot uniformity have been determined during this monitoring period, in order to identify correctable fingerprints. Finally, the dose correction model has been applied to compensate for these systematic CD variations and improved CD control was demonstrated. Using a simple dose correction rule, a forty percent improvement in CD control was obtained.

Effective EUVL mask cleaning technology solutions for mask manufacturing and in-fab mask maintenance

Extreme Ultraviolet Lithography (EUVL) is considered the leading lithography technology choice for semiconductor devices at 16nm HP node and beyond. However, before EUV Lithography can enter into High Volume Manufacturing (HVM) of advanced semiconductor devices, the ability to guarantee mask integrity at point-of-exposure must be established. Highly efficient, damage free mask cleaning plays a critical role during the mask manufacturing cycle and throughout the life of the mask, where the absence of a pellicle to protect the EUV mask increases the risk of contamination during storage, handling and use. In this paper, we will present effective EUVL mask cleaning technology solutions for mask manufacturing and in-fab mask maintenance, which employs an intelligent, holistic approach to maximize Mean Time Between Cleans (MBTC) and extend the useful life span of the reticle. The data presented will demonstrate the protection of the capping and absorber layers, preservation of pattern integrity as well as optical and mechanical properties to avoid unpredictable CD-linewidth and overlay shifts. Experiments were performed on EUV blanks and pattern masks using various process conditions. Conditions showing high particle removal efficiency (PRE) and minimum surface layer impact were then selected for durability studies. Surface layer impact was evaluated over multiple cleaning cycles by means of UV reflectivity metrology XPS analysis and wafer prints. Experimental results were compared to computational models. Mask life time predictions where made using the same computational models. The paper will provide a generic overview of the cleaning sequence which yielded best results, but will also provide recommendations for an efficient in-fab mask maintenance scheme, addressing handling, storage, cleaning and inspection.

Further investigation of EUV process sensitivities for wafer track processing

As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, its shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

Full field EUV lithography: lessons learned on EUV ADT imaging, EUV resist, and EUV reticles

One of the main experimental setups for EUV lithography is the ASML EUV Alpha-Demo Tool (ADT), which achieves the first full-field EUV exposures at a wavelength of 13.6nm and a numerical aperture of 0.25. We report on the assessment of the baseline imaging performance of the ADT installed at IMEC, and review the work done in relation to EUV reticles and resists. For the basic imaging performance of the ADT, we have studied 40 LS patterns through dose and focus and at multiple slit positions, to extract exposure latitude and depth of focus. Measurements of reticle CD vs. wafer CD were done to determine the Mask Error Enhancement Factor (MEEF) for dense features. We also discuss the uniformity of the different features across the field, and the factors that influence it. The progress in EUV resist performance has been tracked by screening new materials on the EUV ADT. Promising resist materials have been tested on the ASML ADT and have demonstrated sub 32nm Line/Space and 34nm dense contact hole resolution. One of the main topics related to EUV reticles is reticle defectivity along with reticle defect printability. We have experimentally measured the number of wafer defects that repeat from die-to-die after reticle exposure on the ADT. To examine the wafer signature of the repeating defects, a SEM-based defect review is then conducted. We have used rigorous simulations to show that the defect signature on wafer can correspond to a relatively large ML defect, which can print as a hollow feature.

Process window discovery methodology development for advanced lithography

With the continued need for shrinking patterning dimensions in semiconductor manufacturing, new lithography techniques, such as advanced multi-patterning, are being introduced into production for 10nm node and beyond, and others, such as EUV, are nearing production requirements. Previous work [1] has shown that these new developments introduce new challenges in terms of qualifying the process window. In the past the boundaries of the overlapping process window (focus and exposure latitude in which all structures in a given layout print within the specifications) were mainly defined by design and OPC related systematic defects and lithographers and defect engineers were relying on Process Window Qualification (PWQ) methods to discover these systematic defects. In more advanced nodes however, the process window is also impacted by FAB related sources (wafer non-uniformity, process variations) or, in case of multi-patterning schemes, also by interactions between the different masks. To take these factors into account PWQ has now evolved into a new methodology called Process Window Discovery (PWD). This paper will focus on further development of this methodology. We will further focus on techniques to enhance the sensitivity of the broadband plasma defect inspection and we will demonstrate how this metrology can highlight intra-field and across-wafer variations. The final step of this work will be to implement this methodology to compare the overlapping process windows of two identical metal layers with 2D logic patterns, of which one layer will be patterned with EUV single patterning and the other will be patterned with 193i triple litho-etch patterning (LE3). For 193i LE3 a special focus goes on the detection of overlay critical hotspots and defining the overlay variation related process window. For EUV special attention goes to EUV specific hotspots and typical sources of variations across wafer.