Fumitake Mieno

Yield improvement using data mining system

It is ideal to prevent all failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasures. There are various types of failures, ranging from the failures due to simple mis-operation to the failures whose cause analysis takes many highly skilled engineers a long time. If the failure cause in the latter case can be specified simply by anyone, the yield enhancement will be accelerated. We are developing a method that enables us to specify a failure cause, without depending on the experience and skills of engineers. Data mining is a method for extracting buried information and rules from data of enormous quantity, by using a statistical method. Some examples have been reported in various fields but only a few in the semiconductor field. This time, we have applied a regression tree analysis system, which is one of data mining tools codeveloped by Fujitsu Laboratories Ltd. and FLT, to failure analysis in LSI manufacturing. As a result, a failure cause which has been difficult to be detected even in the in-process monitoring was specified automatically only in six hours. Then, through the verification process, we ascertained that the failure cause was correct. We could specify the cause and take countermeasures at a speed six times faster than by the conventional method.

Selective Growth of Polysilicon

A chemical vapor deposition (CVD) technique for selective growth of polysilicon has been developed. This technique makes it possible to grow polysilicon only on the exposed silicon without a Si nucleus on the or mask. Perfect selectivity over the whole wafer surface was obtained in a system in the temperature range of 900°–1000°C under a pressure of 100 Pa at a significantly high line velocity. These conditions provide a perfectly selective silicon epitaxy technique, while addition of trichloroethylene as a gas that causes extreme deterioration of the crystallinity produced the selective polysilicon technique without a degradation of selectivity. A SEM observation showed that the grain size of the grown film was about 0.3 μm. SIMS analysis indicated that the concentration of carbon atoms incorporated in the film was on the order of 1020 cm−3. X‐ray rocking curve analysis derived a smaller lattice parameter of 5.425A, due to incorporated carbon atoms.

Novel selective poly - and epitaxial - Silicon growth (SPEG) technique for ULSI processing

We have succeeded in the development of a novel and simple SPEG technique by using Si<inf>2</inf>H<inf>6</inf>as a silicon source gas under a low-pressure (∼8000 Pa) and a low-temperature (∼ 830°C) with no special treatments such as UV-light irradiation or plasma enhancement. SPEG of a 0.2µm-thin film is accomplished with smooth polysilicon surface and good coverage even in the substrate with sharp step of SiO<inf>2</inf>. The defect density of the epitaxial layer is ∼1 cm^-2. Using this new technique, we fabricated successfully the novel bipolar and MOS transistors with contacts over SiO<inf>2</inf>. Even in the low-temperature growth (830°C), 98% bipolar transistors had high BV<inf>CEO</inf>values above 18 V. These results indicate that the epitaxial layer of SPEG have good quality and the polysilicon layer of SPEG is useful for electrode. Our novel SPEG technique produces high-performance ULSIs without any special processes.

Spontaneous Polysilicon and Epitaxial Silicon Deposition

A spontaneous polysilicon and epitaxial silicon deposition (SPED) process for fabricating high performance submicron devices was developed using Si 2 H 6 as a silicon source gas under low pressure and temperature. SPED was achieved at 8000 Pa and 830 o C, even for a 0.2 μm thick film on a substrate with a 0.5 μm SiO 2 step. The defect density of the epilayer was less than 0.3/cm 2 . This SPED layer did not have facets at the transition region

Particle count and analysis by using a cyclone particle sampler

We performed particle composition analysis of clean room particles by using a particle analyzer (PT1000) and a Cyclone Particle Sampler. While we expected to find only small particles in the clean room, we detected many large particles as well. Many floating particles are greatly influenced by air flow current. Particles are created by human movement and we speculate that this is related to air flow. We suggest methods to improve the cleanliness of the clean room and to enhance device yield.

Advanced bipolar process using selective poly- and epitaxial-Si (SPEG) technique

In recent ULSI technology, reduction of parasitic capacitances has been playing an important role in obtaining high speed performance of the devices. SST[lI and SICOS[21 were developed to satisfy this purpose. In these processes, polysilicon base contacts were formed on field oxide and connected with active base region. Therefore, these processes were not so easy. Thus, we have developed SPEG technique which makes it possible to form active region on Si-substrate and contact region on Si02 spontaneous1 using infrared heated barrel reactors. Because, much of the silicon epitaxial growt K done in the,semiconductor industry i s done in,infrared,heated barrel reactors. By using SPEG technique, we have, developed, the slmpler bipolar process which realize the transistor structure reducing arasitic capacitances. We fabricated ECL ring oscillators and evaluated the electrical c c: aracteristics.

Novel dry cleaning using trisilane with a new single-wafer reactor

A single-wafer reactor developed for low-temperature Si/sub 2/H/sub 6/ epitaxy (600 degrees C) and low-temperature Si/sub 3/H/sub 8//H/sub 2/ pretreatment (820 degrees C) is described. The major points covered are (1) the reactors heating system, which uses resistance heating with a SiC-coated graphite susceptor, and (2) the gas ejection system, which provides a high flow velocity and effectively introduces gas to the wafer. Using this reactor, 600 degrees C epitaxial growth was obtained with a 950 degrees C H/sub 2/ bake and growth at 700 AA/min. It was found that Si/sub 3/H/sub 8//H/sub 2/ treatment at 820 degrees C effectively removes oxygen and carbon before epitaxy. The reactor developed provides low-temperature epitaxy for silane without the need for special treatment with, for example, ultraviolet light or plasma.<<ETX>>

ArF photoresist etching behavior evaluation

The transition of photoresist from KrF photoresist to ArF photoresist poses new challenges for etching process, especially for dielectric etching. In this article we design two types of dielectric etching applications, hole (contact) etching and LS (line space) etching. SAS software is employed for DOE (design of experiment) analysis of hole etching process optimization, best condition is derived and confirmed by experiment . To address LER, which is a persistent issue in LS application, mechanism is proposed and LER is successfully solved by new process.

Implementation of double patterning lithography process using limited illumination systems

The double patterning (DP) process is mainly for the resolution enhancement beyond limited lithography system not only high numerical aperture (NA) system but small one also. In this paper, we developed several duty patterns using DP technology under ArF, 0.75 NA systems to meet the 65 nm half-pitch patterns. For the line DP process, it is clear that the limited resolution is 65 nm half pitch pattern with marginal process windows and overlay should be controlled within 30 nm, M+3 sigma value. For the 2nd patterning process, there is dose shift compared with Is patterning dose for the substrate difference. From these results, DP technologies can be applied to overcome resolution limited process not only fine patterning required but certain patterning which can be achieved without any investments.

Rapid Thermal Precleaning Using Hydrogen Reduction

We developed a rapid thermal precleaning technique for using low-temperature hydrogen reduction at 800C. To reduce ttre partial pressure of impurities, we used an ultra high vacuum (UHV) cluster tool with precleaning chamber and a Si deposition chamber. We developed an experimental precleaning chamber that improved the gas flow. Precleaning at 800C for L minute remove oxygen, carbon, and fluorine completely. The contact resistance of poly-SVbulk was 38.9 O with precleaning, and 110.1 O without.