Atsuhiro Tsukune

Ta2O5 thin films with exceptionally high dielectric constant

We have achieved tantalum pentoxide (Ta2O5) thin films with extremely highly predominant 〈001〉 orientation. The Ta2O5 thin films have an exceptionally high dielectric constant of 90–110, and capacitors using these Ta2O5 films as a dielectric layer show the high capacitance and low leakage current meeting the requirements for the new generation of memory devices.

DIFFERENT EFFECT OF ANNEALING TEMPERATURE ON RESISTIVITY FOR STOICHIOMETRIC, W RICH, AND N RICH TUNGSTEN NITRIDE FILMS

The effect of the annealing temperature on the resistivity for stoichiometric (W2N), W rich (x 0.5) tungsten nitride films (WNx) is different. The resistivity of as-deposited W2N is about 230 μΩ cm and it increases slightly and then decreases with increasing the annealing temperature up to 900 °C. However, for the W rich WNx whose initial resistivity before annealing is around 145 μΩ cm, the resistivity monotonically decreases with the annealing temperature increasing from 600 to 900 °C. As to N rich WNx whose initial resistivity is as high as 3000–5000 μΩ cm, though the resistivity must decrease after annealing at 600–750 °C, it irregularly varies at the higher temperature range of 750–900 °C. The different annealing temperature dependence of the resistivity can be explained by considering the nitrogen desorption, conversion of WNx to pure W, and cracking of WNx films.

Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7- µm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff, threshold voltage shift, and junction leakage of transistors. It was found that the electrical properties were not affected by bonding, thinning and debonding process indicating good feasibility of 3D stacking integration to the strain and low-k technology.

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

CONVERSION OF TUNGSTEN NITRIDE TO PURE TUNGSTEN

The properties of W2N thin films deposited on Si, SiO2, and Ta2O5 by plasma-enhanced chemical vapor deposition, with and without an electron cyclotron resonance plasma formed SiO2 (ECR-SiO2) top layer are comparatively investigated. The ECR-SiO2 top layer can effectively promote the conversion of W2N to pure W while samples are annealed at high temperature. After annealing at 900 °C, W2N with the ECR-SiO2 top layer fully converts to W without occurrence of silicidation but that without the ECR-SiO2 top layer partially, or does not convert to W at all. The resistivity for the 900 °C annealed samples with the ECR-SiO2 top layer is only 1/3–1/10 of that without the ECR-SiO2 top layer. The conversion of W2N to W and enhancement of this conversion by the top ECR-SiO2 layer are discussed and explained.

Further Enhancement of Electro-migration Resistance by Combination of Self-aligned Barrier and Copper Wiring Encapsulation Techniques for 32-nm Nodes and Beyond

To further enhance electro-migration resistance, we applied a self-aligned barrier technique to Cu wiring encapsulated with a MnO barrier. This combination of the self-aligned barrier and encapsulation techniques increased maximum current density to 9 times that of the conventional one. The Cu wiring fabricated by the combination of the two techniques also had greater resistance to stress-induced voiding set off by thermal stress. The combination of the two techniques also enhanced the lifetime of time-dependent dielectric breakdown by a factor of 160.

Copper Wiring Encapsulation with Ultra-thin Barriers to Enhance Wiring and Dielectric Reliabilities for 32-nm Nodes and Beyond

We successfully encapsulated Cu wiring with an ultra-thin self-forming barrier consisting of MnO and a bi-layer of MnO/Ta. TDDB test showed that the ILDs lifetime increased by a factor of 100 over that of our control sample. The encapsulated Cu wiring increased EM lifetime by a factor of more than 47. For via chains that are vulnerable to thermal stress, the encapsulated Cu wiring showed no SIV failure. The resistance of the encapsulated Cu wiring was 13% lower than that of the control sample. We expect encapsulated Cu wiring to have greater endurance to the electrical and thermal stresses for use in 32-nm nodes and beyond.

Restraint of Copper Oxidation Using Barrier Restoration Technique with Cu–Mn Alloy

This paper clarifies for the first time that employing Cu–Mn alloy can reduce the resistance of ultralarge scale integration (ULSI) interconnects. It is well known that Cu alloys have higher resistance than pure Cu. However, recent discussion indicates that Cu or barrier metal oxidation by moisture from interlayer dielectrics causes electrical resistance to increase even further. Therefore, Cu oxidation must be prevented. Previously, we have reported a barrier restoration technique using Cu–Mn alloy, and the application of this technique is expected to result in strong tolerance to Cu oxidation. In this work, we investigated the property that copper is protected from oxidation when using the barrier restoration technique with Cu–Mn alloy. This property results in the reduction of interconnect resistance and the improvement of the resistance distribution in ULSI interconnects. We conclude that using the barrier restoration technique with Cu–Mn alloy will be being compatible with further scaling to 22 nm node and beyond.

Advanced BEOL integration using porous low-k (k=2.25) material with charge damage-less electron beam cure technique

As a practical curing technique of low-k material for 32-nm BEOL technology node, we demonstrated that electron beam (e-beam) irradiation was effective to improve film properties of nano-clustering silica (NCS). We confirmed that by using optimized e-beam cure condition, NCS was successfully hardened without degradation of dielectric constant and the Youngs modulus increased by 1.7 times compared with that of thermally cured NCS. We fabricated two-level Cu wirings layers with NCS cured by optimized e-beam cure technique. The e-beam cure dramatically enhanced the lifetime of time-dependent dielectric breakdown (TDDB) of interlayer dielectrics. We also examined the influence of the charge damage to the MOSFETs under e-beam cured NCS layer and confirmed that there was no e-beam charge damage to the Ion-Ioff characteristics and reliability of MOSFETs with the optimized e-beam cure.

Novel dry cleaning using trisilane with a new single-wafer reactor

A single-wafer reactor developed for low-temperature Si/sub 2/H/sub 6/ epitaxy (600 degrees C) and low-temperature Si/sub 3/H/sub 8//H/sub 2/ pretreatment (820 degrees C) is described. The major points covered are (1) the reactors heating system, which uses resistance heating with a SiC-coated graphite susceptor, and (2) the gas ejection system, which provides a high flow velocity and effectively introduces gas to the wafer. Using this reactor, 600 degrees C epitaxial growth was obtained with a 950 degrees C H/sub 2/ bake and growth at 700 AA/min. It was found that Si/sub 3/H/sub 8//H/sub 2/ treatment at 820 degrees C effectively removes oxygen and carbon before epitaxy. The reactor developed provides low-temperature epitaxy for silane without the need for special treatment with, for example, ultraviolet light or plasma.<<ETX>>