Yuko Hanaoka

Resistivity Increase in Ultrafine-Line Copper Conductor for ULSIs

The resistivities of copper (Cu) thin films and damascene Cu fine lines were precisely measured by utilizing Matthiessens rule. It was shown that this measurement method can produce reliable values without requiring precise and detailed line-dimension measurements. It was found that the increase in resistivities of the fine lines is much more than that of the films, and this increase results in an electron mean free path of 45 nm. We propose a simple equation for expressing line resistivity in terms of both line width and line thickness.

Fabricating 3D integrated CMOS devices by using wafer stacking and via-last TSV technologies

A three-layer-stacked wafer with CMOS devices was fabricated for the first time by using hybrid wafer bonding and backside-via-last TSV (7-μm diameter/25-μm length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybrid wafer bonding brings both seamless copper bonding and void-less underfilling in face-to-face (F2F) and back-to-face (B2F) configurations. The backside-via-last TSV processes provide electrical connection between a TSV and copper/low-k interconnects without causing low-k damage. The low capacitance (around 40 fF) of the TSVs results in the highest level of transmission performance (15 Tbps/W) so far. Additionally, according to ring-oscillator measurements, the keep-out-zone (KOZ) is up to 2 μm from a TSV. This extremely small KOZ is mainly attributed to low residual stress in the silicon surrounding a TSV (i.e., below 50 MPa at 2 μm from a TSV edge).

Above-IC integration of capacitive pressure sensor fabricated with CMOS interconnect processes

A surface-micromachined capacitive pressure sensor fabricated with a standard CMOS back-end of line processes was integrated above a CMOS LSI with a sensor front end circuit, and the output signal was obtained via the integrated circuit. The sensor was fabricated using only low-temperature processes and conventional materials and equipment. The sensor measures capacitance and electrical output of the C-V converter integrated on the same substrate with no degradation in signal quality. The sensor was placed above the IC region and sub-half-micron CMOS processes were applied to the IC, so the effective chip size is smaller than 2 mm2. Basic reliability of the sensor was examined. A passivation layer thicker than 150 nm is necessary for suppressing sensitivity change below 1% for the pressure cooker test (120 deg, 100% relative humidity for 100 hr). Our process enables MEMS integrated on any generation CMOS-LSI, enhancing functionality of the sensor chip and minimizing chip size.

Fully CMOS compatible on-LSI capacitive pressure sensor fabricated using standard back-end-of-line processes

A surface micromachined capacitive pressure sensor was fabricated using conventional back-end of line (BEOL) processes in a standard CMOS fabrication line. The combination of standard interlayer dielectric and tungsten was used as sacrificial layers and electrodes, which achieves a large etching selectivity in sacrificial layer removal processes. Measured dependences of capacitance on applied pressure showed a good agreement with simulated results. Although the sensor used metal and amorphous layers in the moving parts (diaphragm), it showed excellent reliability. Sensor characteristics did not change after the deflection test for more than 50M times, temperature cycling test (-55 to 150 deg C, 500 cycles, JEDEC standard) and humidity test (85 deg C, 85% for 100 hr). The process enables us to monolithically integrate MEMS structures with the most advanced CMOS integrated circuits because they use only low temperature processes. Integrating MEMS with high performance digital circuits such as MPU as well as analog circuits enables ultra-tiny one-chip sensor devices.

Thermal stability of nitrogen in WNx barriers applied to polymetal gates

A polymetal gate needs a thin barrier layer for avoiding reactions between the metal layer and the polycrystalline silicon (poly-Si) layer. A tungsten nitride (WNx) barrier is better than a titanium nitride (TiNx) barrier from the viewpoint of thermal resistance to the wet hydrogen oxidizing process in H2O+H2 atmosphere. This oxidizing process is used to recover the integrity of the SiO2 gate oxide film of a metal-oxide-semiconductor transistor, whose electrical characteristics such as breakdown voltage are degraded by the dry etching process for patterning the gate electrode. Nitrogen in WNx barriers formed in N2+Ar using sputtering equipment moves to the surface and the interface with the poly-Si layer in the stacked structure during high-temperature device fabrication processes. As a result, the WNx layer changes into a W layer. We developed a technology for retaining nitrogen in the tungsten nitride barrier layers. The key is that at above 400°C, a WNx layer is formed on the sample when the flowing ra...

One-dimensional-motion and pressure hybrid sensor fabricated and process-level-packaged with CMOS back-end-of-line processes

One-dimensional movable structures (motion sensors) made from a metal silicide (WSi) core were successfully encapsulated inside a cavity in an interlayer dielectric (SiO2) covered by another metallic layer. The latter half of the fabrication process is the same as to that for the pressure sensor that we previously reported [1]; thus, both sensors can be fabricated simultaneously. As is the case with our previously reported pressure sensor, the fabrication processes are compatible with CMOS back-end-of-lines (BEOL) processes (carried out below 400°C). The motion sensor can thus be fabricated directly above integrated circuits (ICs). The fabricated sensors were electrically tested, and the measured pull-in voltage was in good agreement with the design value.

Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration

Successful 3D integration of a stacked chip fabricated by a “chip-level through-silicon-via (TSV)” process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.

Isotropic atomic level etching of tungsten using formation and desorption of tungsten fluoride

A selective, rapid thermal-cyclic atomic-level etching (ALE) of tungsten is developed. The first step of this process is exposing the surface of tungsten with hydrofluorocarbon plasma at −22°C to form a tungsten fluoride-based surface modified layer on the tungsten surface. The second step is rapid thermal annealing with infrared (IR) irradiation to remove the surface modified layer. Tungsten 4f peaks and a fluorine 1s peak, which were assigned to tungsten fluoride, were observed by in-situ x-ray photoelectron spectroscopy immediately after plasma exposure. The peaks that originated from tungsten fluoride disappeared after the samples were annealed. Cyclic etching tests were carried out by repeating plasma exposure and IR irradiation with a 300-mm ALE tool. Films of tungsten, TiN, and SiO2 were used as sample materials. The amount of etched tungsten increased as the number of cycle repetitions increased. The etched amount per cycle for tungsten was 0.8 nm. In comparison, etching of TiN and SiO2 was not detected. Conformal etching profiles of patterned samples after 60 cycles were obtained. Furthermore, the etched amount per cycle showed saturation behavior with regard to plasma exposure time. Selective, rapid thermal cyclic ALE of tungsten was thus successfully demonstrated.

300-Mm wafer 3D integration technology using hybrid wafer bonding

We have developed a low-cost wafer-level three-dimensional (3D) integration technology compatible with 300-mm wafers by using hybrid wafer bonding. This technology includes wafer-to-wafer (W2W) stacking technology with a copper/polymer hybrid wafer bonding and through-silicon via (TSV) reveal process. Bonding of a copper/polymer hybrid wafer achieved good copper-to-copper bonding as well as good polymer-to-polymer bonding without producing any large bonding voids. The misalignment between 300-mm bonding wafers was less than 0.57 μm. Via-middle TSVs (8 μm in diameter and 25 μm in length) were revealed by back grinding (BG) and chemical mechanical polishing (CMP). The electrical connectivity of a three-stacked wafer fabricated by hybrid wafer bonding was confirmed. These results indicate the effectiveness of the proposed 3D integration technology.

Chip-level TSV integration for rapid prototyping of 3D system LSIs

For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called “chip-level TSV integration”) was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.