Kazuyuki Hozawa

Fabricating 3D integrated CMOS devices by using wafer stacking and via-last TSV technologies

A three-layer-stacked wafer with CMOS devices was fabricated for the first time by using hybrid wafer bonding and backside-via-last TSV (7-μm diameter/25-μm length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybrid wafer bonding brings both seamless copper bonding and void-less underfilling in face-to-face (F2F) and back-to-face (B2F) configurations. The backside-via-last TSV processes provide electrical connection between a TSV and copper/low-k interconnects without causing low-k damage. The low capacitance (around 40 fF) of the TSVs results in the highest level of transmission performance (15 Tbps/W) so far. Additionally, according to ring-oscillator measurements, the keep-out-zone (KOZ) is up to 2 μm from a TSV. This extremely small KOZ is mainly attributed to low residual stress in the silicon surrounding a TSV (i.e., below 50 MPa at 2 μm from a TSV edge).

Copper Diffusion Behavior in SiO2/Si Structure During 400°C Annealing

The behavior of copper atoms diffusing from the back surface to the front surface of a silicon wafer during 400°C annealing was examined using total reflection X-ray fluorescence spectrometry. The behavior strongly depended on the back-surface copper concentration and on the front-surface SiO2 thickness. The higher the back-surface copper concentration, the harder it was for the copper to diffuse into the silicon. The number of copper atoms that diffused from the back surface to the front surface was limited by the copper solubility in silicon at 400°C. When the front SiO2 surface was thinner than approximately 3 nm, the atoms easily diffused to the SiO2 surface, but they did not when it was thicker than approximately 3 nm. This difference in the copper diffusion behavior apparently results from whether the SiO2 surface is electrically active or not and indicates that the effect of back-surface copper contamination on the electrical characteristics of semiconductor devices is very small during a back-end process.

Intrinsic Gettering of Copper in Silicon Wafers

We have investigated the intrinsic gettering (IG) of Cu in silicon wafers Oxygen precipitates for IG were formed in wafers subjected to two-step annealing consisting of thermal treatment for 16 h at 800°C. then for 0-16 h at 1000°C. Cu was deposited on the back surface by dipping the wafers into a contaminant solution, and introduced into the wafer bulk from the back surface by heating for 5 min at 1000°C. The surface concentration of Cu was measured by total-reflection X-ray fluorescence. We found that the gettering efficiency, which was determined from the difference between the surface concentration on reference wafers and the corresponding concentration on the IG-treated wafers, depends on the Cu contamination concentration. Moreover, we used a simulation based on the Fokker-Planck equation to analyze the data with regard to the dependence of gettering efficiency on oxygen precipitate density. As a result, we have shown that the total number of oxygen precipitates, rather than their size determines the gettering efficiency. These experimental and calculated results can provide useful information for achieving effective IG of Cu.

Wafer-level hybrid bonding technology with copper/polymer co-planarization

Wafer-level hybrid copper/polymer bonding technology suitable for wafer-level 3D integration (called “thinning after bonding”) was developed. A damascene process is applied for fabricating copper pads. After chemical mechanical polishing (CMP), a globally flat bonding surface is obtained by co-planarization of copper and polymer during barrier CMP. The key to this co-planarization process is optimizing polymer polishing rate by changing polymer cure temperature. As a result of this optimization, copper-copper bonding was achieved, and a seamless polymer-polymer interface was produced. Moreover, a model for local-deformation at the polymer-polymer interface is proposed. This model suggests that the adhesion strength of the bonded polymers is determined by the contact-area ratio of the polymers under thermocompression.

True influence of wafer-backside copper contamination during the back-end process on device characteristics

The influence of backside Cu contamination during the back-end process on the electrical characteristics of MOSFETs was revealed. The influence is well explained in terms of Cu diffusion behavior at 400/spl deg/C, which strongly depends on SiO/sub 2/ thickness at front and back sides of wafers. Cu atoms brought into the Si wafer can not diffuse into the thick front-side SiO/sub 2/ film, but Cu atoms exist inside Si near the SiO/sub 2//Si interface after annealing. Accordingly, backside Cu contamination during the back-end process does not affect Time Zero Dielectric Breakdown (TZDB), Dit, or Vfb, but it decreases Time Dependent Dielectric Breakdown (TDDB) lifetime and drastically enhances short-channel effect due to impurity compensation.

Copper distribution near a SiO2/Si interface under low-temperature annealing

In relation to the thickness of a surface SiO2 film, the behavior of copper atoms existing at the SiO2/Si interface during low-temperature annealing (≤400°C) is investigated by an analytical method combining step-etching and multi-angle total reflection of X-ray fluorescence. It is shown that SiO2 thickness plays an important role in the re-distribution of copper. For a 2-nm-thick SiO2 film, copper diffused from the interface to the SiO2 surface. On the other hand, in a 5-nm-thick SiO2 film, copper diffused toward the bulk. This copper re-distribution behavior also affected the electrical characteristics, such as Dit and Vth, of the metal-oxide-semiconductor (MOS) capacitors. The degradation of oxide breakdown characteristics after 400°C annealing suggests that copper atoms move around in the SiO2 film before leaving the interface.

Void reduction in wafer bonding by simultaneously formed ventilation channels

We introduced two techniques for reducing formation of voids in wafer-level hybrid bonding with copper and polymer. As for the first technique, the amount of voids was reduced without any additional processes by forming ventilation channels simultaneously with the bump layer. As a result, dicing yield of 100% was achieved. As for the second technique, post-CMP annealing prevents breakage of bonded wafers after thinning during annealing.

Evaluation of damage induced by electron beam irradiation to MOS gate pattern and method for damage- free inspection

We analyzed the electron-irradiation damage induced in wafers by SEM inspection, which uses SEM images of voltage contrast formed by the charges on the pattern due to the electron irradiation. MOS capacitors were selected as samples because of their characteristic sensitivity. We studied the effects of electron-beam energy and charging on a MOS-capacitor test element group. To determine flat-band voltage, density of created traps, and oxide fixed charges in the MOS capacitors before and after the irradiations of the capacitors by electron beams under various conditions, we measured high-frequency and quasi-static capacitance-voltage characteristics. We found that the higher-energy electron beam, whose electron range was larger than the thickness of the gate electrode, created traps at the interface between the silicon substrate and the gate dielectric. The flat-band voltage of the MOS capacitor was shifted by the created traps. Although these traps were created by the transmission of the electron beam into the dielectric, they were not created only by charging on the gate electrode; neither was an oxide fixed charge created in the MOS capacitor. Accordingly, for damage-free inspection of MOS devices, the electron-beam energy should be low enough that the electron range is smaller than the thickness of the gate electrode. On the other hand, the flat-band voltage did not shift owing to charging on the pattern surface during the electron irradiation. However, the gate dielectric was broken down by charging on the gate electrode at high voltage. Accordingly, for damage-free inspection, the charging voltage should be controlled so as not to break down the gate dielectric.

Copper distribution behavior near a SiO/sub 2//Si interface by low-temperature (<400/spl deg/C) annealing and its influence on electrical characteristics of MOS-capacitors

The Cu redistribution behavior near a SiO/sub 2//Si interface after low temperature annealing is examined by using total reflection of X-ray fluorescence (TXRF) to simulate the effect of thermal budget in multi-level wiring processes. Cu atoms intentionally adsorbed on backside of the wafers were diffused and were once gettered at the gettering sites during high-temperature drive-in diffusion. However, after low-temperature annealing following the drive-in diffusion, Cu concentration of the Si surface was found to increase even in CZ wafers with intrinsic gettering process (IG). Cu atoms gettered in the vicinity of the SiO/sub 2//Si interface after drive-in diffusion are found to readily transport through the SiO/sub 2/ film and reach the SiO/sub 2/ surface during 400/spl deg/C annealing. This transport of Cu is found to cause degradation of thin SiO/sub 2/ film. The redistribution phenomenon during low-temperature annealing should be carefully controlled in order to realize highly reliable CMOS devices.

Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration

Successful 3D integration of a stacked chip fabricated by a “chip-level through-silicon-via (TSV)” process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.