G. Bertolone

CMOS pixel sensor development: a fast read-out architecture with integrated zero suppression

CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated their strong potential for tracking devices, particularly for flavour tagging. They are foreseen to equip several vertex detectors and beam telescopes. Most applications require high read-out speed, which imposes sensors to feature digital output with integrated zero suppression. The most recent development of MAPS at IPHC and IRFU addressing this issue will be reviewed. The design architecture, combining pixel array, column-level discriminators and zero suppression circuits, will be presented. Each pixel features a preamplifier and a correlated double sampling (CDS) micro-circuit reducing the temporal and fixed pattern noises. The sensor is fully programmable and can be monitored. It will equip experimental apparatus starting data taking in 2009/2010.

A reticle size CMOS pixel sensor dedicated to the STAR HFT

ULTIMATE is a reticle size CMOS Pixel Sensor (CPS) designed to meet the requirements of the STAR pixel detector (PXL). It includes a pixel array of 928 rows and 960 columns with a 20.7 μm pixel pitch, providing a sensitive area of ~ 3.8 cm2. Based on the sensor designed for the EUDET beam telescope, the device is a binary output sensor with integrated zero suppression circuitry featuring a 320 Mbps data throughput capability. It was fabricated in a 0.35 μm OPTO process early in 2011. The design and preliminary test results, including charged particle detection performances measured at the CERN-SPS, are presented.

MISTRAL & ASTRAL: two CMOS Pixel Sensor architectures suited to the Inner Tracking System of the ALICE experiment

A detector, equipped with 50 μm thin CMOS Pixel Sensors (CPS), is being designed for the upgrade of the Inner Tracking System (ITS) of the ALICE experiment at LHC. Two CPS flavours, MISTRAL and ASTRAL, are being developed at IPHC aiming to meet the requirements of the ITS upgrade. The first is derived from the MIMOSA28 sensor designed for the STAR-PXL detector. The second integrates a discriminator in each pixel to improve the readout speed and power consumption. This paper will describe in details the sensor development and show some preliminary test results.

A ten thousand frames per second readout MAPS for the EUDET beam telescope

Designed and manufactured in a commercial CMOS 0.35 μm OPTO process for equipping the EUDET beam telescope, MIMOSA26 is the first reticule size pixel sensor with digital output and integrated zero suppression. It features a matrix of pixels with 576 rows and 1152 columns, covering an active area of ~224 mm. A single point resolution of about 4 μm was obtained with a pixel pitch of 18.4 μm. Its architecture allows a fast readout frequency of ~10 k frames/s. The paper describes the chip design, test and major characterisation outcome.

Intermediate Digital Monolithic Pixel Sensor for the EUDET High Resolution Beam Telescope

A high resolution beam telescope, based on CMOS Monolithic Active Pixels Sensors (MAPS), is being developed under the EUDET collaboration, a coordinated detector R&D program for a future international linear collider. A very good spatial resolution < 5 mum, a fast readout time of 100 mus for the whole array (136 times 576 pixels) and a high granularity can be obtained with this technology. A recent fast MAPS chip, designed in AMS CMOS 0.35 mum Opto process with 14 mum epitaxial layer and called MIMOSA22, was submitted to foundry. MIMOSA22 has an active area of 26.5 mm2 with a pixel pitch of 18.4 mum arranged in an array of 576 rows by 136 columns where 8 columns have analog test outputs and 128 have their outputs connected to offset compensated discriminator stages. The pixel array is divided in seventeen blocks of pixels, with different amplification gain, diode size, pixel architecture and is addressed row-wise through a serially programmable (JTAG) sequencer. Discriminators have a common adjustable threshold with internal DAC. MIMOSA22 is the last chip (IDC-Intermediate Digital Chip), before the final sensor of the EUDET-JRA1 beam telescope, which will be installed on the 6 GeV electron beam line at DESY. In this paper, laboratory test results on analog and digital parts are presented. Test beam results, obtained with a 120 GeV pion beam at CERN, are also presented. In the last part of the paper, results on irradiated chips are given.

A Digital Monolithic Active Pixel Sensor Chip in a Quadruple-Well CIS Process for Tracking Applications

A CMOS sensor chip for charged particle detection has been developed and submitted for fabrication in a 0.18 μm Quadruple-Well (N&P-Wells, Deep N&P-Wells) CMOS Image Sensor (CIS) process. Improvement of the radiation hardness, the power dissipation and the readout speed of the mainstream CMOS sensors is expected with the exploration of this process. In order to ensure better charge collection and neutron tolerance, wafers with high-resistivity epitaxial layer have been chosen. In this paper a digital CMOS sensor prototype developed in order to validate the key analog blocks (from sensing element to 1-bit digital conversion) of a binary Monolithic Active Pixel Sensor (MAPS) in this process will be presented. The digital sensor prototype comprises four different sub-arrays of 20 μm pitch 64 × 32 pixels, 128 column-level auto-zeroed discriminators, a sequencer and an output digital multiplexer. Laboratory tests results including the charge-to-voltage conversion factor, the charge collection efficiency, the temporal noise and the fixed-pattern noise are presented in details. Some irradiation results will also be given.

Design and Characterisation of a Fast Architecture Providing Zero Suppressed Digital Output Integrated in a High Resolution CMOS Pixel Sensor for the STAR Vertex Detector and the EUDET Beam Telescope

CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated their strong potential for tracking devices, particularly for flavour tagging. They are foreseen to equip several vertex detectors and beam telescopes. Most applications require high read-out speed, imposing sensors to feature digital output with integrated zero suppression. The most recent development of MAPS at IPHC and IRFU addressing this issue will be reviewed. An architecture will be presented, combining a pixel array, column-level discriminators and zero suppression circuits. Each pixel features a preamplifier and a correlated double sampling (CDS) micro-circuit reducing the temporal and fixed pattern noises. The sensor is fully programmable and can be monitored. It will equip experimental apparatus starting data taking in 2009/2010.

Development of the MISTRAL & ASTRAL sensors for the upgrade of the Inner Tracking System of the ALICE experiment at LHC

A detector, equipped with 50 um thin CMOS Pixel Sensors (CPS), is being designed for the upgrade of the Inner Tracking System (ITS) of the ALICE experiment at LHC. Two CPS flavours, MISTRAL and ASTRAL, are being developed at IPHC aiming to meet the requirements of the ITS upgrade. The first is derived from the MIMOSA28 sensor designed for the STAR-PXL detector. The second, which integrates a discriminator in each pixel, improves the readout speed and power consumption. This paper will describe in details the sensor development and show some preliminary test results.

A Radiation Hard Digital Monolithic Pixel Sensor for the EUDET-JRA1 Project

In the framework of the EUDET-JRA1 project (European Detector R&D towards the International Linear Collider), which consists of design, realization and implantation of a high resolution beam digital telescope, based on Monolithic Active Pixel Sensors (MAPS), an intermediate digital chip sensor, MIMOSA22, has already been delivered with good detection performances. Although this intermediate chip has fulfilled all the initial requirements of the project, it was admitted that radiation tolerance behavior of the sensor could be improved, especially if the high precision telescope is used later in a hadron testbeam infrastructure. For this purpose, a new version of the sensor, MIMOSA22-BIS, has been designed, with several improved pixel architectures, and using the same AMS 0.35 μm opto process of the sensor MIMOSA22. This paper will be focused on tests performed in laboratory conditions using a 55Fe source, and tests performed in CERN-SPS, using a 120 GeV pion beam, in order to characterize detection performances of the chip with MIPs, before and after ionizing irradiation.

IMIC — needle-shaped low-power monolithic active pixel sensor for molecular neuroimaging on awake and freely moving rats

IMIC is a Monolithic Active Pixel Sensor prototype for the MAPSSIC project dedicated to direct detection of low energy β+ rays in the brain of awake and freely-moving rats using CMOS technology. Former experiments using a β+ Si probe developed within the PIXSIC project validated a methodological proof of concept. However, conducting routinely such measurements would require improvements with respect to the passive pixel sensors employed in PIXSIC. The new IMIC circuit is fabricated in a 180 nm CMOS Image Sensor Technology and features a matrix of 16 × 128 pixels, which are 30 × 50 μm2 large. The sensor has a needle-like aspect ratio (610 μm × 12 000 μm). The chip is produced on a 18 μm high-resistivity epitaxial layer substrate. The foreseen application requires high sensitivity to β-rays while being immune to background γ-rays. Another severe constraint is the limited power dissipation in order to minimize the thermal impact on the brain. IMIC is a fully-programmable digital sensor. The pixel design is based on the front-end architecture of the ALPIDE chip. However modifications have been made to store the information inside fired pixels between two readouts allowing low data throughput. The circuit is controlled through the SPI protocol, which allows for setting all the necessary polarization signals. The results of post-layout simulations show a high signal to noise ratio (>40) and low power dissipation of 115 μW/matrix. Laboratory characterization using β-rays validate these predictions and demonstrated that the slow readout can cope with the expected low activity (≍ 120 hits/matrix/s).