G. Fontana

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a CMOS 0.13 μm process. The optimization of the collecting electrode geometry and the re-design of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely “APSEL3T1” and “APSEL3T2”. The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55Fe and electrons from 90Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip “APSEL4D”, having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.

Proposal of a data sparsification unit for a mixed-mode MAPS detector

The Italian silicon-detectors-with-low-interaction-with material collaboration (SLIM5) has designed, fabricated and tested several prototypes of CMOS monolithic active pixel sensors (MAPS). This paper shows the design of a new mixed-mode chip prototype composed of a bidimensional matrix of pixels, and of an off-pixel digital readout sparsification circuit. The readout logic is based on commercial standard cells and implements an optimized non token readout technique. Also, a MAPS emulator software toool is presented. The project is aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future high-energy physics experiments. The readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers on tracks in vertex detectors.

Recent development on triple well 130 nm CMOS MAPS with in-pixel signal processing and data sparsification capability

A different approach to the design of CMOS MAPS has recently been proposed. By exploiting the triple well option of a CMOS commercial process, a deep n-well (DNW) MAPS sensor has been realized with a full in-pixel signal processing chain: charge preamplifier, shaper, discriminator and a latch. This readout approach beeing compatible with data sparsification will improve the readout speed potential of MAPS sensors. The first protoype chips, realized with STMicroelectronics 130 nm triple well process, proved the new design proposed for DNW MAPS is viable with a good sensitivity to photons from 55Fe and electrons from 90Sr. Extensive tests performed to characterize the second generation of the APSEL chips based on the DNW MAPS design are reported. Small 3times3 pixel matrices with full analog output have been tested with radioactive sources to characterize charge collection. Pixel noise equivalent charge (ENC) of 50 e- and signal-to-noise ratio for MIPs of about 14 have been measured. Improved pixel noise and reduced threshold dispersion (about 100 e-) have been measured in the 8times8 matrix with a sequential readout. Based on the new DNW MAPS design a dedicated fast readout architecture to perform on-chip data sparsification is currently under development. The aim is to incorporate in the same detector the advantages of the thin CMOS sensors and similar functionalities as in hybrid pixels.

Development of 130nm CMOS Monolithic Active Pixels with In-pixel Signal Processing

We developed monolithic active pixel detectors that exploit the triple well option of CMOS 130 nm technology to implement analog and digital signal processing at the pixel level. The charge collecting element is realized using the deep N-well (DNW) and partially overlaps the analog circuit. With this scheme we were able to implement a full in-pixel signal processing chain, composed of a charge preamplifier, shaper, discriminator, and latch. This approach has been validated by a first prototype (APSEL0), and we report here on the extensive measurements performed on the second prototype (APSEL1), containing various single pixel structures with analog readout and an 8 times 8 matrix of 50 times 50 mum2 pixels with sequential digital readout. For 900 mum2 pixels the equivalent noise charge has been measured to be 40 e-, with a S/N ratio of about 30 for the 55Fe 5.9 keV signal. The matrix readout has been tested up to 30 MHz and the crosstalk between pixels characterized. The threshold dispersion and the noise of the pixels in the matrix have been measured through noise scans. These measurements confirm the viability of the triple well process for MAPS fabrication, and indicate the design improvements for the next prototype chip (APSEL2).

2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker

The high luminosity asymmetric e+e− collider SuperB, recently approved by the Italian Government, is designed to deliver a luminosity greater than 1036cm−2s−1 with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with an innermost layer of small radius (about 1.5 cm), resolution of 10 µm in both coordinates, low material budget (< 1% X0), and able to withstand a hit background rate of several tens of MHz/cm2. The ambitious goal of designing a thin pixel device matching these stringent requirements is being pursued with specific R&D programs on different technologies: CMOS MAPS, pixel sensors in vertical integration technology and hybrid pixels with small pitch and reduced material budget. The latest results on the characterization of the various pixel devices realized for the SuperB Layer0 will be presented.

On-Chip Fast Data Sparsification for a Monolithic 4096-Pixel Device

The paper describes a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensors (MAPS). The matrix has 128 columns and 32 rows of pixels and is divided into 256 regions of 4 times 4 pixels, named macro-pixels (MPs). The chip is an upgrade of a smaller version having 256 pixels that was designed and tested. The two chips were designed via STM 130 nm CMOS technology. The pixel dimension is 50 by 50 mum2 . The work is aimed at improving the design of MAPS detectors with an on-chip fast sparsification system, for particle tracking, to match the requirements of future high-energy physics experiments. The readout architecture implemented is data driven to extend the flexibility of the system, to be also used in first level triggers on tracks in vertex detectors. Simulations indicate that the readout system can cope with an average hit rate up to 100 MHz/cm2 if a master clock of 80 MHz is used, while maintaining an overall efficiency over 99%.

Thin pixel development for the Layer0 of the SuperB Silicon Vertex Tracker

The SuperB asymmetric e⁺ e⁻ collider has been designed to deliver a luminosity greater than 10³⁶ cm⁻² s⁻¹ maintaining moderate beam currents. Comparing to current B-Factories, the reduced center-of-mass boost of the SuperB machine requires an improved vertex resolution to allow precision measurements sensitive to New Physics. Therefore the SuperB Silicon Vertex Tracker will be equipped with an innermost Layer0 with a radius of about 1.5 cm, high granularity, low material budget and able to withstand a background rate of several MHz/cm². We report on the status of the R&D on the different options under study for the Layer0: DNW MAPS, hybrid pixels and thin pixels developed with vertical integration technology.