G. Giacomini

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a CMOS 0.13 μm process. The optimization of the collecting electrode geometry and the re-design of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely “APSEL3T1” and “APSEL3T2”. The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55Fe and electrons from 90Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip “APSEL4D”, having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.

Recent development on triple well 130 nm CMOS MAPS with in-pixel signal processing and data sparsification capability

A different approach to the design of CMOS MAPS has recently been proposed. By exploiting the triple well option of a CMOS commercial process, a deep n-well (DNW) MAPS sensor has been realized with a full in-pixel signal processing chain: charge preamplifier, shaper, discriminator and a latch. This readout approach beeing compatible with data sparsification will improve the readout speed potential of MAPS sensors. The first protoype chips, realized with STMicroelectronics 130 nm triple well process, proved the new design proposed for DNW MAPS is viable with a good sensitivity to photons from 55Fe and electrons from 90Sr. Extensive tests performed to characterize the second generation of the APSEL chips based on the DNW MAPS design are reported. Small 3times3 pixel matrices with full analog output have been tested with radioactive sources to characterize charge collection. Pixel noise equivalent charge (ENC) of 50 e- and signal-to-noise ratio for MIPs of about 14 have been measured. Improved pixel noise and reduced threshold dispersion (about 100 e-) have been measured in the 8times8 matrix with a sequential readout. Based on the new DNW MAPS design a dedicated fast readout architecture to perform on-chip data sparsification is currently under development. The aim is to incorporate in the same detector the advantages of the thin CMOS sensors and similar functionalities as in hybrid pixels.

The associative memory for the self-triggered SLIM5 silicon telescope

Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly exclusive selections to efficiently select the rare events inside the huge background. We present a fast, high-quality, track-based event selection for the self-triggered SLIM5 silicon telescope. This is an R&D experiment whose innovative trigger will show that high rejection factors and manageable trigger rates can be achieved using fine-granularity, low-material tracking detectors.

Development of 130nm CMOS Monolithic Active Pixels with In-pixel Signal Processing

We developed monolithic active pixel detectors that exploit the triple well option of CMOS 130 nm technology to implement analog and digital signal processing at the pixel level. The charge collecting element is realized using the deep N-well (DNW) and partially overlaps the analog circuit. With this scheme we were able to implement a full in-pixel signal processing chain, composed of a charge preamplifier, shaper, discriminator, and latch. This approach has been validated by a first prototype (APSEL0), and we report here on the extensive measurements performed on the second prototype (APSEL1), containing various single pixel structures with analog readout and an 8 times 8 matrix of 50 times 50 mum2 pixels with sequential digital readout. For 900 mum2 pixels the equivalent noise charge has been measured to be 40 e-, with a S/N ratio of about 30 for the 55Fe 5.9 keV signal. The matrix readout has been tested up to 30 MHz and the crosstalk between pixels characterized. The threshold dispersion and the noise of the pixels in the matrix have been measured through noise scans. These measurements confirm the viability of the triple well process for MAPS fabrication, and indicate the design improvements for the next prototype chip (APSEL2).

Functional characterization of a high-gain BJT radiation detector

n-p-n bipolar phototransistors have been designed and fabricated on high-resistivity silicon substrates. A technology featuring a double implant for the emitter allowed us to obtain a typical current gain of about 600. The device has been tested with /spl alpha/ particles from a /sup 239/Pu source, /spl beta/ particles from /sup 90/Sr, and X-rays from /sup 241/Am using a simple experimental setup, where the detector is directly connected to the oscilloscope. In the case of electrons, pulse heights of 100 mV have been observed, with pulse length of 50 /spl mu/s, measured on a load resistor in series to the emitter. The parameters driving the time performance have been measured, obtaining a good agreement with the electrical model of the device. We report on the functional characterization of the device, in particular the time response, the energy calibration, and the electronic noise measurement.

Application of the BJT detector for simple, low-cost, and low-power alpha-particle detection systems

We present a simple, low-cost, and low-power alpha-particle detection system for environmental radioactivity monitoring. The system exploits a previuosly-developed high- resistivity-silicon detector with internal amplification capability based on the bipolar-transistor (BJT) effect and readout electronics based on commercial ICs. Two-dimensional numerical device simulations are adopted to assess the feasibility of the BJT detector as an alpha-particle detector that can be operated, without losing its internal signal amplification capability, with floating base and low collector voltages, so that device technology can be kept simple, very small DC power consumption can be achieved, and a single 5-V power-supply voltage can be used for readout electronics and detector biasing. The charge amplification accomplished by the BJT detector allows a single, commercial chip to be adopted, to perform charge preamplification and 20-bit A/D conversion. The digital output is sent to a low-cost microcontroller that can be periodically interrogated through the IR port. The cost of the readout electronics is in the order of 60

Noise Characterization of Double-Sided Silicon Microstrip Detectors With Punch-Through Biasing

and it can operate with standard Li-ion battery for about 60 hours.

Radon alpha-ray detector based on a high-resistivity-silicon BJT and a low-cost readout electronics

We report on extensive noise measurements performed on double-sided, AC-coupled, punch-through biased silicon strip detectors. We used a single-channel acquisition chain, reading one strip per side, all other strips being kept grounded. The noise has been measured over a wide range of peaking times and leakage currents, allowing a careful determination of the various noise contributions. We determined the noise contribution of the punch-through mechanism and we observed, on different sensors, two unexpected noise terms, one related to the punch-through current and the other to the presence of resistive layers at the Si/SiO2 interface.

Development of 3D detectors at FBK-irst

Radon dosimetry yields valuable information about radioactive health risks in closed environments. Indeed, World Health Organization (WHO) and the International Agency for Research on Cancer (IARC) have recently classified radon as a human carcinogen and have demonstrated a correlation between environmental radon concentration and lung cancer risk. Dose measurements are traditionally based on laboratory analysis of alpha-ray traces in ionization chambers exposed to environmental air. In this paper we propose a portable instrument for real-time radon alpha-ray detection based on a previously-developed high-resistivity-silicon BJT sensor and a low-cost, IC-based readout electronics.

Double-sided strip sensors for the Limadou-CSES project

We report on the development of 3D detectors at Fondazione Bruno Kessler - irst in the framework of the CERN RD-50 Collaboration. Technological and design aspects dealing with the 3D Single Type Column detectors are reviewed, and selected results from the electrical and functional characterization of prototypes are reported and discussed. A new detector concept, namely 3D Double-side Double Type Column detectors, allowing for significant performance enhancement while maintaining a reasonable process complexity, is final ly addressed.