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Dive into the research topics where Gabriel Kittler is active.

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Featured researches published by Gabriel Kittler.


international symposium on industrial electronics | 2010

Optimization of trench manufacturing for a new high-voltage semiconductor technology

Matthias Fritzsch; M. Schramm; Klaus Erler; Steffen Heinz; John T. Horstmann; Uwe Eckoldt; Gabriel Kittler; Ralf Lerner; Klaus Schottmann

Deep trenches for device insulation in a high-voltage process in thick SOI were fabricated using different manufacturing technologies. The trenches have been investigated by current-voltage-characteristics. In comparison to the conventional produced trenches alternatively fabricated samples reach a remarkable increase of the breakdown voltages accompanied by a decline of the leakage current in the order of several magnitudes. Respecting other process parameters a trench fabrication method has been selected which enables the manufacturing of reliable single trenches suitable for operating voltages up to 650 V. The new trench can be implied within a prospective X-FAB process. A reduction of area consumption is possible in many designs by replacing double trenches by single trenches. The future high-voltage X-FAB process will include new primitive devices which are currently designed and characterized. In this work new diode types with characteristic properties are presented.


2011 Semiconductor Conference Dresden | 2011

Device engineering for a modular 650 V transistor assortment

Ralf Lerner; Klaus Schottmann; Gabriel Kittler

Using a trench isolated 650 V quasi-vertical n-channel DMOS as a starting point several new 650 V transistor types have been evaluated. Mainly by design measures a 650 V depletion DMOS, a 650 V PMOS and a 650 V IGBT were created for a modular integration into the process flow. Design modifications like increased channel length, well constructions and drain modifications were used to create the new devices. Original n-channel DMOS design features like curvatures or field plate constructions have been re-used. Necessary new process steps for the depletion transistor and for the IGBT were kept to minimum additional process effort and use a flexible process approach with independent addable modules.


international soi conference | 2010

Single trench isolation for a 650 V SOI technology with low mechanical stress

Gabriel Kittler; Ralf Lerner; Uwe Eckoldt; Klaus Schottmann; Matthias Fritzsch; M. Schramm; Klaus Erler; Steffen Heinz; John T. Horstmann

The successful optimization and characterization of a deep trench isolation in a thick SOI process for operating voltages up to 650 V is reported. Different technologies were investigated to optimize the mechanical stress during wafer processing and to increase the breakdown voltage of a single trench configuration. Comprehensive electrical characterization was done to investigate achievable operating conditions and related reliability issues for thick oxide trench isolation layers. The most promising trench technology was choosen as a modular extension to an existing 650 V SOI BCD process.


Archive | 2010

Method for Producing Silicon Semiconductor Wafers Comprising a Layer for Integrating III-V Semiconductor Components

Gabriel Kittler; Ralf Lerner


Archive | 2010

Method for fabricating semiconductor wafers for the integration of silicon components with hemts, and appropriate semiconductor layer arrangement

Gabriel Kittler; Ralf Lerner


Archive | 2011

Verfahren zur Herstellung von Siliziumhalbleiterscheiben mit III-V-Schichtstrukturen für die Integration von Siliziumbauelementen mit auf Gruppe III-V-Schichtstrukturen basierenden High Electron Mobility Transistoren (HEMT) und entsprechende Halbleiterschichtanordnung

Gabriel Kittler; Ralf Lerner


Archive | 2010

DMOS Transistor Having an Increased Breakdown Voltage and Method for Production

Ralf Lerner; Phil Hower; Gabriel Kittler; Klaus Schottmann


Archive | 2011

Verfahren zur Herstellung von Siliziumhalbleiterscheiben mit Schichtstrukturen zur Integration von III-V Halbleiterbauelementen

Gabriel Kittler; Ralf Lerner


Archive | 2010

Planar high-voltage transistor i.e. laterally diffused metal oxide semiconductor transistor, for integrated smart power switching circuit, has oxide bar whose length on region of interconnect structure is larger than width of structure

Gabriel Kittler; Astrid Küffner; Ralf Lerner


Archive | 2013

DMOS-Transistor mit erhöhter Durchbruchsspannung und Verfahren zur Herstellung.

Ralf Lerner; Hower, Phil, Tex.; Gabriel Kittler; Klaus Schottmann

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John T. Horstmann

Chemnitz University of Technology

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Klaus Erler

Chemnitz University of Technology

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M. Schramm

Chemnitz University of Technology

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Matthias Fritzsch

Chemnitz University of Technology

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Steffen Heinz

Chemnitz University of Technology

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