Gage Hills

Carbon nanotube computer

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.

Three-dimensional integration of nanotechnologies for computing and data storage on a single chip

The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors—promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage—fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce ‘highly processed’ information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.

Energy-Efficient Abundant-Data Computing: The N3XT 1,000x

Next-generation information technologies will process unprecedented amounts of loosely structured data that overwhelm existing computing systems. N3XT improves the energy efficiency of abundant-data applications 1,000-fold by using new logic and memory technologies, 3D integration with fine-grained connectivity, and new architectures for computation immersed in memory.

Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs

Low-power applications, such as sensing, are becoming increasingly important and demanding in terms of minimizing energy consumption, driving the search for new and innovative interface architectures and technologies. Carbon nanotube FETs (CNFETs) are excellent candidates for further energy reduction, as CNFET-based digital circuits are projected to achieve an order of magnitude improvement in energy-delay product compared with silicon-CMOS at highly scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to imperfections and variations such as those induced by mispositioned and metallic CNTs. These substantial imperfections and variations have prevented the demonstration of complex CNFET circuits until now. This paper presents the first demonstration of a subsystem, which is a complete capacitive sensor interface circuit, implemented entirely using CNFETs that can be fabricated reproducibly in a VLSI-compatible fashion. This is made possible by: 1) a digitally oriented interface architecture and 2) the imperfection-immune design paradigm, which combines design and processing techniques to successfully overcome CNT imperfections and variations. In addition to electrical measurements, we demonstrate correct operation of our CNFET circuitry by interfacing it with a sensor used to control a handshaking robot.

High-performance carbon nanotube field-effect transistors

We demonstrate carbon nanotube (CNT) field-effect transistors (CNFETs) with the highest current drive (per unit layout width)¹ to-date (>100 μA/μm at 400 nm channel length and 1V V_DS), while simultaneously achieving high I_ON/I_OFF (>5,000). This is the first demonstration of CNFETs with CNT density above 100 CNTs/μm consisting of highly-aligned CNTs and achieving both high current drive and high I_ON/I_OFF. The current drives of the demonstrated CNFETs approach that of similarly-scaled and similarly-biased silicon-based field-effect transistors in production in major semiconductor foundries.

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad hoc techniques. In this paper, we present a framework that quickly evaluates the impact of CNT variations on circuit delay and noise margin, and systematically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that our framework: 1) runs over 100× faster than existing approaches and 2) accurately identifies the most important CNT processing parameters, together with CNFET circuit design parameters (e.g., for CNFET sizing and standard cell layouts), to minimize the impact of CNT variations on CNFET circuit speed with ≤5% energy cost, while simultaneously meeting circuit-level noise margin and yield constraints.

Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs

This paper presents a complete sensor interface implemented entirely using CNFETs that can be fabricated reproducibly in a VLSI-compatible fashion. This is made possible by using the imperfection-immune paradigm [4], which successfully overcomes major obstacles for CNFET-based circuits: mis-positioned and metallic carbon nanotubes (CNTs). 44 CNFETs, each consisting of 10 to 200 CNTs depending on transistor sizing, are used to build the circuit. In contrast, earlier demonstrations of CNFET-based circuits included only small stand-alone components such as an adder sum, latch, percolation transport-based decoder, and ring oscillator on a single CNT [4]. Because it is easier to implement digital circuits using immature technologies compared to analog circuits, highly-digital sensor interfaces such as the PLL-based design in [5] are ideal implementations when using a new technology. The implemented capacitive sensor interface is based on a first-order Bang-Bang Phase-Locked Loop (BBPLL) digital architecture, which processes the sensor information entirely in the frequency domain (Fig. 6.8.1). Its funcationality is described in detail in [5].

Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution.

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in todays silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly-scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad-hoc techniques. In this paper, we present a systematic framework which quickly evaluates the impact of CNT variations on circuit delay and noise margin, and automatically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that: 1. Our new framework runs over 100X faster than existing approaches. 2. It accurately identifies the most important CNT processing parameters, together with CNFET circuit sizing, to minimize the impact of CNT variations while meeting circuit-level noise margin constraints.

Efficient metallic carbon nanotube removal for highly-scaled technologies

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise to improve the performance and energy efficiency of digital systems beyond the limitations of silicon CMOS, the presence of metallic CNTs (m-CNTs) remains a major challenge. Existing techniques for removing m-CNTs are inadequate, as they face one or more of the following scalability challenges: scaling to large circuits (≥99.99% of m-CNTs must be removed without inadvertently removing semiconducting CNTs, s-CNTs), scaling to short channel lengths (for highly-scaled contacted gate pitch (CPP)), and scaling to small inter-CNT spacing (for high CNT densities required for high CNFET ION). We demonstrate a new m-CNT removal technique that, for the first time, overcomes all of these scalability challenges, as it: (a) removes ≥99.99% of m-CNTs vs. ≤1% of s-CNTs, (b) scales to any arbitrary CPP, and (c) scales to high CNT densities (≥200 CNTs/μm).