Chi-Shuen Lee

Energy-Efficient Abundant-Data Computing: The N3XT 1,000x

Next-generation information technologies will process unprecedented amounts of loosely structured data that overwhelm existing computing systems. N3XT improves the energy efficiency of abundant-data applications 1,000-fold by using new logic and memory technologies, 3D integration with fine-grained connectivity, and new architectures for computation immersed in memory.

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements

We present a data-calibrated compact model of carbon nanotube (CNT) FETs (CNTFETs) based on the virtual-source (VS) approach, describing the intrinsic current-voltage and charge-voltage characteristics. The features of the model include: 1) carrier VS velocity extracted from experimental devices with gate lengths down to 15 nm; 2) carrier effective mobility and velocity depending on the CNT diameter; 3) short channel effect such as inverse subthreshold slope degradation and drain-induced barrier lowering depending on the device dimensions; and 4) small-signal capacitances including the CNT quantum capacitance effect to account for the decreasing gate capacitance at high gate bias. The CNTFET model captures the dimensional scaling effects and is suitable for technology benchmarking and performance projection at the sub-10-nm technology nodes.

Compact Model for Carbon Nanotube Field-Effect Transistors Including Nonidealities and Calibrated With Experimental Data Down to 9-nm Gate Length

A semianalytical carbon nanotube field-effect transistor (CNFET) model based on the virtual-source model is presented, which includes series resistance, parasitic capacitance, and direct source-to-drain tunneling leakage. The model is calibrated with recent experimental data down to 9-nm gate length. Device performance of 22- to 7-nm technology nodes is analyzed. The results suggest that contact resistance is the key performance limiter for CNFETs; direct source-to-drain tunneling results in significant leakage due to low effective mass in carbon nanotubes and prevents further downscaling of the gate length. The design space that minimizes the gate delay in CNFETs subject to OFF-state leakage current (IOFF) constraints is explored. Through the optimization of the length of the gate, contact, and extension regions to balance the parasitic effects, the gate delay can be improved by more than 10% at 11- and 7-nm technology nodes compared with the conventional 0.7 × scaling rule, while the OFF-state leakage current remains below 0.5 μA/μm .

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part II: Extrinsic Elements, Performance Assessment, and Design Optimization

We present a data-calibrated compact model of carbon nanotube (CNT) FETs (CNFETs), including contact resistance, direct source-to-drain, and band-to-band tunneling currents. The model captures the effects of dimensional scaling and performance degradations due to parasitic effects, and is used to study the tradeoffs between the drive current and the leakage current of CNFETs according to the selection of CNT diameter, CNT density, contact length, and gate length for a target contacted gate pitch. We describe a co-optimization study of CNFET device parameters near the limits of scaling with physical insight, and project the CNFET performance at the 5-nm technology node with an estimated contacted gate pitch of 31 nm. Based on the analysis, including parasitic resistance, capacitance, and tunneling leakage current, a CNT density of 180 CNTs/μm will enable the CNFET technology to meet the International Technology Roadmap for Semiconductors target of drive current (1.33 mA/μm), which is within reach of modern experimental capabilities.

1D Selection Device Using Carbon Nanotube FETs for High-Density Cross-Point Memory Arrays

A novel one-transistor-n-resistors (1TnR) array architecture is demonstrated as a cost-effective solution to the sneak path problem in large-scale cross-point memory arrays. In a 1TnR array, a single transistor (1T) with a 1D channel effectively controls a number of resistive switching nonvolatile memory (NVM) cells (nR) while limiting the sneak leakage current within the 1D channel without sacrificing the device density. To maximize these benefits, a carbon nanotube FET (CNFET) is employed as the 1D selection device, due to its near-ballistic electrical transport properties even at a small device width. Experimental demonstrations of the CNFET-based 1TnR concept are presented with two promising resistive switching NVM candidates: 1) resistive random access memory (RRAM) and 2) phase-change memory (PCM). Here, we report that the integrated bipolar Al2O3-based RRAM consumes programming energies as low as 0.1-7 pJ per bit and has a high programming endurance of up to 106 cycles. The 1TnR RRAM cell also has self-compliance characteristics, because the semiconducting carbon nanotube (CNT) that serves as the bottom electrode limits the device current. The unipolar PCM cells integrated with CNFETs show uniform electrical characteristics with high ON-/OFF-resistance ratios of >10. Owing to the extremely small contact area between the phase change material, Ge2Sb2Te5, and the CNT, remarkably low programming currents of <;1 μA are achieved.

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad hoc techniques. In this paper, we present a framework that quickly evaluates the impact of CNT variations on circuit delay and noise margin, and systematically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that our framework: 1) runs over 100× faster than existing approaches and 2) accurately identifies the most important CNT processing parameters, together with CNFET circuit design parameters (e.g., for CNFET sizing and standard cell layouts), to minimize the impact of CNT variations on CNFET circuit speed with ≤5% energy cost, while simultaneously meeting circuit-level noise margin and yield constraints.

Carbon nanotube circuits: opportunities and challenges

Carbon Nanotube Field-Effect Transistors (CNFETs) are excellent candidates for building highly energy-efficient digital systems. However, imperfections inherent in carbon nanotubes (CNTs) pose significant hurdles to realizing practical CNFET circuits. In order to achieve CNFET VLSI systems in the presence of these inherent imperfections, careful orchestration of design and processing is required: from device processing and circuit integration, all the way to large-scale system design and optimization. In this paper, we summarize the key ideas that enabled the first experimental demonstration of CNFET arithmetic and storage elements. We also present an overview of a probabilistic framework to analyze the impact of various CNFET circuit design techniques and CNT processing options on system-level energy and delay metrics. We demonstrate how this framework can be used to improve the energy-delay-product (EDP) of CNFET-based digital systems.

A 1TnR array architecture using a one-dimensional selection device

Phase-change memory (PCM) cells on a single carbon nanotube field-effect transistor (CNFET) are demonstrated toward the realization of the 1TnR array architecture. The use of CNFET as one-dimensional selector, which exhibits ultra-low leakage (<; 1 pA) and large ON/OFF ratio (> 106) at high current densities, enables the cost-effective PCM cell to operate with a wide voltage margin in large 2D arrays. Uniform electrical characteristics of PCM cells over 100 cycles are obtained with the ON/OFF ratio of ~ 100 and the low SET/RESET currents of <; 1 μA.

Compact modeling and design optimization of carbon nanotube field-effect transistors for the sub-10-nm technology nodes

Summary form only given. Single-wall semiconducting carbon nanotube (CNT) field-effect transistors (CNFETs) have been among the foremost candidates to complement Si and extend CMOS technology scaling to sub-10-nm technology thanks to the atomically thin body of CNTs and their near-ballistic transport [1-3]. However, non-idealities such as high contact resistance (Rc) [4], parasitic capacitance and tunneling leakage current can diminish the superior intrinsic electrical properties of CNTs in a highly scaled CNFET. Here we present the first data-calibrated compact model for CNFETs which captures dimensional scaling effects, metal-CNT contact resistance, parasitic capacitance, and direct source-to-drain tunneling leakage current. We then use this model to study design trade-offs and identify the remaining critical challenges for the CNFET technology. The model has been implemented in Verilog-A, is now available online [5], and will be described here for the first time.

Compact models of emerging devices

Compact modeling of resistive switching memory (RRAM) and carbon nanotube field-effect transistor (CNFET) are presented. The models are suitable for exploration of device design space, assessment of device performance at the circuit level. Optimization of the CNFET device structure to minimize the gate delay is presented as a demonstration of the models capability. Simulation of neuromorphic computation system is an example application of the RRAM model. The models can be used to perform advance explorations of circuits and sub-systems of emerging devices prior to the availability of reliable, high-yielding fabrication processes for the emerging devices.