Tony F. Wu

Energy-Efficient Abundant-Data Computing: The N3XT 1,000x

Next-generation information technologies will process unprecedented amounts of loosely structured data that overwhelm existing computing systems. N3XT improves the energy efficiency of abundant-data applications 1,000-fold by using new logic and memory technologies, 3D integration with fine-grained connectivity, and new architectures for computation immersed in memory.

Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

We demonstrate monolithic 3D integration of logic and memory in arbitrary vertical stacking order with the ability to use conventional inter-layer vias to connect between any layers of the 3D IC. We experimentally show 4 vertically-stacked layers (logic layer followed by two memory layers followed by another logic layer), enabled by the integration of traditional silicon-FETs (on the bottom-most layer) with low-processing-temperature emerging nanotechnologies: metal-oxide resistive random-access memory (RRAM), and carbon nanotube-FETs (CNFETs). As a demonstration, we show a routing element of a switchbox for a field-programmable gate array (FPGA), with each component of the routing element (involving both logic and memory elements) on their own vertical layer.

Carbon Nanotube Circuit Integration up to Sub-20 nm Channel Lengths

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.

Biophysical Influence of Airborne Carbon Nanomaterials on Natural Pulmonary Surfactant

Inhalation of nanoparticles (NP), including lightweight airborne carbonaceous nanomaterials (CNM), poses a direct and systemic health threat to those who handle them. Inhaled NP penetrate deep pulmonary structures in which they first interact with the pulmonary surfactant (PS) lining at the alveolar air-water interface. In spite of many research efforts, there is a gap of knowledge between in vitro biophysical study and in vivo inhalation toxicology since all existing biophysical models handle NP-PS interactions in the liquid phase. This technical limitation, inherent in current in vitro methodologies, makes it impossible to simulate how airborne NP deposit at the PS film and interact with it. Existing in vitro NP-PS studies using liquid-suspended particles have been shown to artificially inflate the no-observed adverse effect level of NP exposure when compared to in vivo inhalation studies and international occupational exposure limits (OELs). Here, we developed an in vitro methodology called the constrained drop surfactometer (CDS) to quantitatively study PS inhibition by airborne CNM. We show that airborne multiwalled carbon nanotubes and graphene nanoplatelets induce a concentration-dependent PS inhibition under physiologically relevant conditions. The CNM aerosol concentrations controlled in the CDS are comparable to those defined in international OELs. Development of the CDS has the potential to advance our understanding of how submicron airborne nanomaterials affect the PS lining of the lung.

TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

There are increasing concerns about possible malicious modifications of integrated circuits (ICs) used in critical applications. Such attacks are often referred to as hardware Trojans. While many techniques focus on hardware Trojan detection during IC testing, it is still possible for attacks to go undetected. Using a combination of new design techniques and new memory technologies, we present a new approach that detects a wide variety of hardware Trojans during IC testing and also during system operation in the field. Our approach can also prevent a wide variety of attacks during synthesis, place-and-route, and fabrication of ICs. It can be applied to any digital system, and can be tuned for both traditional and split-manufacturing methods. We demonstrate its applicability for both application-specified integrated circuits and field-programmable gate arrays. Using fabricated test chips with Trojan emulation capabilities and also using simulations, we demonstrate: 1) the area and power costs of our approach can range between 7.4%-165% and 7%-60%, respectively, depending on the design and the attacks targeted; 2) the speed impact can be minimal (close to 0%); 3) our approach can detect 99.998% of Trojans (emulated using test chips) that do not require detailed knowledge of the design being attacked; 4) our approach can prevent 99.98% of specific attacks (simulated) that utilize detailed knowledge of the design being attacked (e.g., through reverse engineering); and 5) our approach never produces any false positives, i.e., it does not report attacks when the IC operates correctly.

Cooling three-dimensional integrated circuits using power delivery networks

Our comprehensive analysis, over a range of 3D integration methods and application power density characteristics, quantifies major benefits of PDNs on the temperature distribution of 3D ICs. For example, PDNs can reduce the maximum steady-state temperature by over 35 °C for a 2-layer monolithic 3D IC. Our OpenSPARC T2 case study also demonstrates that the cooling benefits of PDNs are essential to achieve monolithic 3D integration. Our analysis framework can be adopted for exploring technology-circuit-application interactions for a wide variety of 3D technologies, cooling options, PDN designs, or even software-level task scheduling approaches. Of course, it is essential to experimentally validate the simulation results presented in this paper.

Efficient metallic carbon nanotube removal for highly-scaled technologies

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise to improve the performance and energy efficiency of digital systems beyond the limitations of silicon CMOS, the presence of metallic CNTs (m-CNTs) remains a major challenge. Existing techniques for removing m-CNTs are inadequate, as they face one or more of the following scalability challenges: scaling to large circuits (≥99.99% of m-CNTs must be removed without inadvertently removing semiconducting CNTs, s-CNTs), scaling to short channel lengths (for highly-scaled contacted gate pitch (CPP)), and scaling to small inter-CNT spacing (for high CNT densities required for high CNFET ION). We demonstrate a new m-CNT removal technique that, for the first time, overcomes all of these scalability challenges, as it: (a) removes ≥99.99% of m-CNTs vs. ≤1% of s-CNTs, (b) scales to any arbitrary CPP, and (c) scales to high CNT densities (≥200 CNTs/μm).

Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition

The ability to learn from few examples, known as one-shot learning, is a hallmark of human cognition. Hyperdimensional (HD) computing is a brain-inspired computational framework capable of one-shot learning, using random binary vectors with high dimensionality. Device-architecture co-design of HD cognitive computing systems using 3D VRRAM/CMOS is presented for language recognition. Multiplication-addition-permutation (MAP), the central operations of HD computing, are experimentally demonstrated on 4-layer 3D VRRAM/FinFET as non-volatile in-memory MAP kernels. Extensive cycle-to-cycle (up to 1012 cycles) and wafer-level device-to-device (256 RRAMs) experiments are performed to validate reproducibility and robustness. For 28-nm node, the 3D in-memory architecture reduces total energy consumption by 52.2% with 412 times less area compared with LP digital design (using registers as memory), owing to the energy-efficient VRRAM MAP kernels and dense connectivity. Meanwhile, the system trained with 21 samples texts achieves 90.4% accuracy recognizing 21 European languages on 21,000 test sentences. Hard-error analysis shows the HD architecture is amazingly resilient to RRAM endurance failures, making the use of various types of RRAMs/CBRAMs (1k ∼ 10M endurance) feasible.

Monolithic 3D integration advances and challenges: From technology to system levels

Recent technological advances in monolithic 3D integration lay the foundation for highly efficient next-generation computing systems. These advances, however, can only be utilized to their full potential if system architectures are properly optimized by utilizing monolithic 3D-IC technology for target applications. Thus, a multidisciplinary research framework from system architecture to technology layers, and several experimental demonstrations are required.

Monolithic 3D integration: a path from concept to reality

Monolithic three-dimensional (3D) integration enables revolutionary digital system architectures of computation immersed in memory. Vertically-stacked layers of logic circuits and memories, with nano-scale inter-layer vias (with the same pitch and dimensions as tight-pitched metal layer vias), provide massive connectivity between the layers. The nano-scale inter-layer vias are orders of magnitude denser than conventional through silicon vias (TSVs). Such digital system architectures can achieve significant performance and energy efficiency benefits compared to todays designs. The massive vertical connectivity makes such architectures particularly attractive for abundant-data applications that impose stringent requirements with respect to low-latency data processing, high-bandwidth data transfer, and energy-efficient storage of massive amounts of data. We present an overview of our progress toward realizing monolithic 3D ICs, enabled by recent advances in emerging nanotechnologies such as carbon nanotube field-effect transistors and emerging memory technologies such as Resistive RAMs and Spin-Transfer Torque RAMs.