Gain Kim

A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces

An efficient signaling scheme for serial-data transceivers (TRXs) has been proposed, which can properly reduce inter-symbol interference (ISI) and crosstalk (Xtalk) in memory interfaces. The proposed architecture relies on fully-digital implementation rather than analog/multi-tone approach, which can offer a very power-efficient and versatile silicon implementation. Moreover, the Xtalk induced noise can be fairly reduced by applying the proposed signaling, and the whole TRX can customize to the communication link trough digital calibration, while the aggregate data rate is kept fixed.

Architectural modeling of a single-sideband wireline serial data transceiver for multi-drop I/O

This paper presents a wireline serial data transceiver (TRX) architecture employing a concept of single-sideband (SSB) modulation to transmit data over a multi-drop (MD) electrical link with deep notches. The proposed TRX utilizes channel notch as a filter to remove one sideband of the power spectrum of the upconverted signal, thereby reducing the bandwidth occupancy by half. After downconversion is performed by a mixer on the receiver (RX) side, the original baseband (BB) signal can be recovered without loss of any information as long as the upconverted signal does not experience severe distortion by other notches. Simulation results show that the proposed TRX can transmit up to 6.4-Gb/s data stream over a reference MD channel of which the first notch is located at 2.5-GHz without any equalization circuit, while conventional TRX with non-return to zero (NRZ) signaling requires CTLE and at least 5-tap DFE for data rate above 5-Gb/s, to open the eye on the receiver side.

Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data links

This paper presents a serial link transceiver (TRX) architecture that enables high-speed data transmission over a lossy backplane channel without the presence of equalization circuits. The proposed architecture employs multi-tone signaling to reduce inter-symbol interference (ISI) and to increase receiver (RX) timing margin. A single-sideband (SSB) modulation has also been employed for saving of required bandwidth per sub-channel, so as to minimize inter-channel interference (ICI). System-level simulation results show that the proposed TRX can easily transmit 20 Gb/s data stream over a lossy backplane channel that exhibits 28-dB attenuation at 10 GHz while requiring neither of continuous-time linear equalizer (CTLE) and decision feedback equalizer (DFE). By transmitting 3-to-5 Gb/s data stream over each of four sub-channels, at least 44% unit interval (UI) eye openings are achieved for all sub-channels when 20 Gb/s aggregate data is transmitted.

A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces

A transceiver (TRX) architecture employing a spectrum shaping signaling scheme is proposed, which can significantly reduce intersymbol interference and crosstalk in multidrop interfaces. The proposed TRX architecture relies on digital implementation rather than an analog/multitone approach, which can offer a power-efficient and versatile silicon implementation. Moreover, the crosstalk-induced noise can be reduced by applying the spectrum shaping signaling, and the whole TRX can be customized to the communication link by digital calibration while the aggregate data rate is kept fixed.

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cancelled out by decision-feedback equalizer (DFE). However, due to the existence of feedback loop in DFE, there is no trivial way to parallelize it, making it difficult to be realized in digital circuits for wireline RX based on analog-to-digital converter (ADC) with ≥ 56 Gb/s data rate. In this work, convolution theorem is applied for achieving parallel digital equalizer implementation. The digital equalizer datapath consists of discrete Fourier transform (DFT) core, inverse-DFT (IDFT) core, complex multipliers between DFT and IDFT cores, and overlap-add circuit. Design considerations for low-area VLSI implementation of such architecture is discussed.

Analysis, optimization, and modeling of analog multi-tone serial data transceivers

This paper presents a versatile and fast time-domain architectural modeling framework for high-speed serial data transceivers (TRX) that can employ various analog modulation schemes. We highlight a modeling of TRXs employing an analog multi-tone signaling, which is not straightforward to model and hard to optimize with conventional serial link modeling tools. A method to limit the computing systems memory usage when simulating a data transmission of a long bit-stream, e.g., greater than 10 Mbits, is also described. The reliability of the modeling framework is proven by some comparisons with a highly-trusted commercial tool for a conventional TRX architecture.

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links

A time-division multiplexing digital channel coding scheme with inter-channel interference reduction property for multi-drop memory interfaces has been proposed. Shaping the transmitter output spectrum to avoid channel frequency notches, the proposed digital time-domain multiplexing signaling reduces inter-symbol interference and far-end crosstalk in multi-drop bus interfaces. Thanks to a proper guard interval insertion, the transmitted signal exhibits reduced inter-channel interference among time-domain sub-channels, as compared to the previously proposed digital spectrum shaping signaling. Applying the proposed coding scheme, the data rate can be four times as high as the first channel notch frequency, without employing decision-feedback equalizer, feed-forward equalizer, and continuous-time linear equalizer. On the other hand, non-return-to-zero signaling necessitates decision-feedback equalizer with at least 12 taps on the receiver side for receiving data at the same rate for the same multi-drop bus interface.

Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme

This paper presents the design and analysis of a serial link transceiver (TRX) architecture employing analog multi-tone signaling for chip-to-chip communication. Multi-tone single-sideband signaling scheme is proposed in TRX architecture in order to optimize bandwidth requirements for each sub-channel and to improve signal-to-noise ratio by reducing inter-channel interferences (ICI) between neighboring sub-channels. System-level modeling results show that the proposed TRX architecture enables equalizer-free communication at 16 Gb/s over a lossy backplane channel that exhibits 22-dB attenuation at 8 GHz, while conventional non-return-to-zero signaling TRX necessitates a two-stage continuous-time linear equalizer. A channel frequency-response inversion scheme, the up/down-conversion mechanism of the TX/RX data stream and the RX design considerations have been analyzed and investigated by architectural modeling.

Design optimization of polyphase digital down converters for extremely high frequency wireless communications

In this paper, an area-optimized polyphase digital down converter (DDC) architecture is introduced, where the mixers can be completely merged into the polyphase decimation filter under certain conditions. We also introduce an interface architecture, called synchronizer, between the back-end of an extremely high-speed time interleaved ADC (TI-ADC) and the front-end of a polyphase DDC. The synchronizer enables safe downsampling for a polyphase DDC, when the TI-ADCs sampling rate is above tens of GS/s. We show that the proposed interface architecture prevents any potential timing constraint violations that might occur in the interface between a TI-ADC and a polyphase DDC for extremely high frequency (EHF) wireless communication applications.