Kiarash Gharibdoust

Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces

A 7.5 Gb/s mixed NRZ/multi-tone (NRZ/MT) transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for an MDB channel with 45 dB loss at 2.5 GHz. The transmitted spectrum is composed of baseband (BB) and I/Q sub-bands with the ability to match the modulation frequency of the entire transceiver (TRX) with respect to the channel response over a ±25% range. A switched-capacitor-based mixer/filter is developed to efficiently down convert and equalize the I/Q sub-bands in the RX. The core size area is 85 × 60 μm2 and 150 × 60 μm2 for the TX and RX, respectively.

10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS

Advancements in CMOS technology have enabled exponential growth of computational power. However, data processing efficiency also relies on sufficient data communication bandwidth between different units of a computing system. Memory systems typically apply dual in-line memory modules (DIMMs) because of their high capacity and low cost. However, the multi-drop bus (MDB) interface between these units and the controller is challenging for bandwidth and power reasons. Multi-tone signaling has promising characteristics for this type of interface [1]. To keep up with the ever growing demand for higher bandwidth in multi-drop buses, we develop a 7.5Gb/s (3.75Gb/s/pin) NRZ/multi-tone (NRZ/MT) transceiver with a total link power efficiency of 1mW/Gb/s.

A Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects

A low-power 4-channel hybrid NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. The proposed system achieves 1 pJ/bit power efficiency, while communicating over an MDB channel with 45 dB loss at 3 GHz. The multi-tone (MT) nature of the proposed transceiver helps to control the intersymbol interference (ISI) and reduce the far-end crosstalk (FEXT), which results in a very energy-efficient implementation. The core size area is 80 x 60 um2 and 130 x60 um2 for the TX and RX blocks (including the clock unit), respectively.

A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces

An efficient signaling scheme for serial-data transceivers (TRXs) has been proposed, which can properly reduce inter-symbol interference (ISI) and crosstalk (Xtalk) in memory interfaces. The proposed architecture relies on fully-digital implementation rather than analog/multi-tone approach, which can offer a very power-efficient and versatile silicon implementation. Moreover, the Xtalk induced noise can be fairly reduced by applying the proposed signaling, and the whole TRX can customize to the communication link trough digital calibration, while the aggregate data rate is kept fixed.

A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces

A transceiver (TRX) architecture employing a spectrum shaping signaling scheme is proposed, which can significantly reduce intersymbol interference and crosstalk in multidrop interfaces. The proposed TRX architecture relies on digital implementation rather than an analog/multitone approach, which can offer a power-efficient and versatile silicon implementation. Moreover, the crosstalk-induced noise can be reduced by applying the spectrum shaping signaling, and the whole TRX can be customized to the communication link by digital calibration while the aggregate data rate is kept fixed.

A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS

An aggregated 36 Gb/s low power 4-lanes mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40nm CMOS technology. The proposed architecture achieves 1 pJ/bit power efficiency in the entire link (TX + RX) for an MDB channel with 45 dB loss at 3 GHz. The multi-tone nature of the proposed transceiver is employed to properly reduce crosstalk (Xtalk) induced noise and to improve overall power efficiency.

Analysis, optimization, and modeling of analog multi-tone serial data transceivers

This paper presents a versatile and fast time-domain architectural modeling framework for high-speed serial data transceivers (TRX) that can employ various analog modulation schemes. We highlight a modeling of TRXs employing an analog multi-tone signaling, which is not straightforward to model and hard to optimize with conventional serial link modeling tools. A method to limit the computing systems memory usage when simulating a data transmission of a long bit-stream, e.g., greater than 10 Mbits, is also described. The reliability of the modeling framework is proven by some comparisons with a highly-trusted commercial tool for a conventional TRX architecture.

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links

A time-division multiplexing digital channel coding scheme with inter-channel interference reduction property for multi-drop memory interfaces has been proposed. Shaping the transmitter output spectrum to avoid channel frequency notches, the proposed digital time-domain multiplexing signaling reduces inter-symbol interference and far-end crosstalk in multi-drop bus interfaces. Thanks to a proper guard interval insertion, the transmitted signal exhibits reduced inter-channel interference among time-domain sub-channels, as compared to the previously proposed digital spectrum shaping signaling. Applying the proposed coding scheme, the data rate can be four times as high as the first channel notch frequency, without employing decision-feedback equalizer, feed-forward equalizer, and continuous-time linear equalizer. On the other hand, non-return-to-zero signaling necessitates decision-feedback equalizer with at least 12 taps on the receiver side for receiving data at the same rate for the same multi-drop bus interface.

Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme

This paper presents the design and analysis of a serial link transceiver (TRX) architecture employing analog multi-tone signaling for chip-to-chip communication. Multi-tone single-sideband signaling scheme is proposed in TRX architecture in order to optimize bandwidth requirements for each sub-channel and to improve signal-to-noise ratio by reducing inter-channel interferences (ICI) between neighboring sub-channels. System-level modeling results show that the proposed TRX architecture enables equalizer-free communication at 16 Gb/s over a lossy backplane channel that exhibits 22-dB attenuation at 8 GHz, while conventional non-return-to-zero signaling TRX necessitates a two-stage continuous-time linear equalizer. A channel frequency-response inversion scheme, the up/down-conversion mechanism of the TX/RX data stream and the RX design considerations have been analyzed and investigated by architectural modeling.

A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS

This paper presents the design and implementation of a multiplying delay-locked loop (MDLL) in 40 nm bulk CMOS process, which can be used as clock and data recovery (CDR) unit in source-synchronous wire-line communications. The MDLL multiplies the reference frequency and delivers differential in-phase (I) and quadrature (Q) clocks by generating 8 equally spaced clock phases and combining these phases appropriately. A technique for reducing deterministic jitter (DJ) in MDLL is proposed. The prototype dissipates 1.1-1.8 mW over output frequency range of 2.6-6.4 GHz, while the RMS jitter and I/Q mismatch remain below 3 psrms and ±5°, respectively, over the entire range. The core size occupies 60 × 40 μm2 silicon area.