Armin Tajalli

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.

Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS

While the general trend in CMOS technology scaling is mostly focused on high-performance and high-speed circuits, the potential use of advanced nanoscale technologies for ultra-low power (ULP) applications with lower operating frequencies is still debated. In these types of applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, recent studies show that reducing the supply voltage increases the device susceptibility to process variations, resulting in delay spread and decreased noise margin. This article presents an analytical approach for studying the effect of technology scaling and variability on performance of ULP integrated systems. Unlike the conventional design methodologies, we include the effect of process variation on circuit performance (such as on noise margin and delay) in each step of design and optimization. Here, the power dissipation and noise margin are both calculated as a function of turn-on and turn-off current of devices. This approach helps to explore the effect of these two quantities on performance of CMOS digital circuits. The trade-offs between the choice of supply voltage, threshold voltage, device dimensions, delay performance, activity rate, and power consumption are analytically examined using predictive device models, for different technology nodes. Taking into account the circuit reliability requirements, this analysis can be used to optimize the system performance with proper device sizing and selecting supply voltage.

A Slew Controlled LVDS Output Driver Circuit in 0.18

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 mum CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 Omega resistor with an output voltage swing of VOD = 400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 mm2 and the measured output jitter is sigmarms = 4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load RC time constant.

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This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold regime, the circuit can be used in a very wide frequency range by adjusting the bias current without any need for resizing the devices. Measurements in 0.18 mum CMOS technology show that the proposed MCML circuit can be operated reliably with bias currents as low as 1 nA offering a significant improvement of the power-delay product compared to conventional CMOS gates. Simulations show that the proposed circuit exhibits faster response compared to the conventional MCML circuits with triode-mode PMOS load devices at low bias currents.

m CMOS Technology

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 mum CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of 0.045 mm2 /channel, with the total aggregate data bit rate of 20 Gb/s. The measured FTOL is plusmn3.5% and no error was detected for a 231-1 pseudo-random bit stream (PRBS) input data for 30 minutes, meaning that the bit error rate (BER) is smaller than 10-12. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning range and compensated loop gain has been introduced to tune the center frequency of all CDR channels to the desired value.

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

This brief presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. Based on the proposed approach, a source-follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18-mum CMOS technology show an improvement by a factor of as high as 2.4 in power-delay product (PDP). It is also shown that the proposed technique can be used for implementing subthreshold ultra-low power SCL logic gates with a better power and area efficiency, compared to the traditional SCL subthreshold circuits. An optimized approach is proposed to improve the power efficiency of ultra-low power STSCL library cells.

A Power-Efficient Clock and Data Recovery Circuit in 0.18

A sixth-order low-pass transconductor-C filter with a very wide tuning range (fc = 100 Hz to 10 MHz) is presented. The wide tuning range has been achieved without using switchable components or programmable building blocks. A single-stage folded cascode transconductor is employed to implement the proposed filter. A modified biquadratic topology is introduced to improve linearity performance of the filter over its tuning range. Power consumption of the filter scales linearly with cutoff frequency (60 pW/Hz/pole). Implemented in 0.18-μm complementary metal-oxide-semiconductor technology, the filter exhibits relatively constant noise and linearity performance over its entire tuning range and occupies a silicon area of 0.16 mm2 (0.027 mm2/pole).

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The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS circuits is more pronounced, subthreshold SCL (STSCL) can be used effectively for reducing the power consumption. An STSCL-based static random-access memory (SRAM) array has been implemented to demonstrate the performance of this topology for ultra-low-power consumption and low-activity-rate digital circuits. A novel 9T memory cell has been developed to reduce the stand-by (leakage) current to 10pA/cell while the SRAM array is operating at 2.1MHz clock frequency. The power consumption benefits of the proposed circuit style can be maintained in nanometer CMOS technology nodes.

CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

A 7.5 Gb/s mixed NRZ/multi-tone (NRZ/MT) transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for an MDB channel with 45 dB loss at 2.5 GHz. The transmitted spectrum is composed of baseband (BB) and I/Q sub-bands with the ability to match the modulation frequency of the entire transceiver (TRX) with respect to the channel response over a ±25% range. A switched-capacitor-based mixer/filter is developed to efficiently down convert and equalize the I/Q sub-bands in the RX. The core size area is 85 × 60 μm2 and 150 × 60 μm2 for the TX and RX, respectively.

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits

This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed technique is based on using subthreshold source-coupled or current-mode approach for both analog and digital circuits. In addition to possibility of operating with ultra-low power dissipation, because of similar basis for constructing analog and digital parts, a common power management unit could be used for optimizing the power-performance of the entire mixed-signal system. Some circuit examples have been provided to show the performance of the proposed circuits in practice.