Gary LaFontant

Design optimization for isolation in high wiring density packages with high speed SerDes links

This paper discusses design tradeoffs for high speed signal performance in buildup laminate packages with high wiring density. Trace design in die escaping area, PTH vias placement pattern and BGA I/O assignments are analyzed in depth for design optimization through numerous simulations as major areas of high coupling concern and channel performance. Then design suggestions are made at each area for performance and cost optimization and design strategies are developed to achieve the overall required performance as a whole system. Lastly some coupling test results on HSS links are presented to verify the performance of the design

Novel design and integration enhancements in the final polymeric passivation for improved mechanical performance and C4 electromigration in lead-free C4 products

Two key C4 reliability concerns for the current and next generation integrated circuits are electromigration (EM) and “white C4” bumps caused by the stresses induced by die-package interactions. This paper discusses novel design and integration changes in the final polymeric passivation via (FV) in order to mitigate white bump and chip-package interaction (CPI) stresses in the ultra-low k (ULK) BEOL levels and also meet lead-free C4 EM requirements. FV design changes such as strategically offsetting a single or multiple FV vias towards the center of the chip and thus to the compressive side of the C4 bump has been shown to reduce the stresses in the ULK levels due to chip package interactions and hence significantly reduce the number of white bump fails. Changing the shape of the FV via to strategically distribute current more uniformly through the C4 bumps has also been shown to improve the C4 EM performance significantly, while lowering the overall stresses in the chip. Effects of final passivation thickness and via diameter on the white bump stresses will also be discussed. Supporting white-bump, C4 EM and electrical/mechanical modeling data showing the benefits of the design and integration changes will also be discussed in detail in the paper.

Packaging the Cell Broadband Engine microprocessor for supercomputer applications

The Cell Broadband Enginetrade (Cell BE) processor initially designed for high-end consumer electronics, has been enhanced by IBM for supercomputer applications. The enhancements to the chip also necessitated the design and development of a new package. The modifications to the chip included replacement of the 3.2 Gb/s XDR interface with a 800 Mb/s DDR2 interface of equal bandwidth. This required the addition of several hundred chip-level connections (C4s) and package BGA balls. Incorporating this and other enhancements to the chip resulted in a ~20% larger chip and a larger and more complex package. Additional noise from this large memory interface also drove decoupling requirements that necessitated mounting capacitors on both the top and bottom sides of the package. This paper describes the design of this new package as well as the analysis and characterization techniques used to address the packaging concerns outlined above. It includes a comprehensive noise analysis as well as a thorough characterization of the DDR2 interface in the final prototypes. The paper also outlines the design and analysis of the power distribution to the various voltage domains on the chip. Along with electrical design and performance, the paper also includes finite element modeling of the mechanical stresses resident in this FCPBGA package. Finally, the concluding portions of the paper will discuss the trade-offs between electrical performance and mechanical stability, reliability and relative cost.

AC operation of high performance glass ceramic package interconnect and impact on manufacturing

Ceramic packages for high performance server processors have many wiring layers and via count due to the large number of input-output (I/Os) needed in high end computers to attain performance targets. Good AC operation of the interconnect is critical to attain since long traces and vias can be very lossy in these applications. The electrical impact of manufacturing changes implemented in these modules due to mechanical, thermal, or yield issues can be difficult to discern due to the large number of structures and parameter variation in the package. In addition, most of the signals in modern processors operate at a fundamental frequency well into the gigahertz range making traditional direct current (DC) electrical measurements less meaningful to designers and process development engineers. We quantify the AC electrical impact of package manufacturing changes using a high speed microwave vector network analyzer (VNA) on the module interconnects. We measure the effect of several of these changes on various ceramic multi-chip modules (MCM) as a function of frequency. We show how these measurements have lead to a modified cross section in high performance glass ceramic (HPGC) packages used for IBM large scale server processors.

Design-performance aspects of Glass Ceramic in comparison to Alumina Ceramic and organic FCPBGA packages for high link densities of high speed SerDes

High performance glass ceramic (HPGC) packages widely used in various range of IBM server applications are characterized for high frequency performance of SerDes differential links using TDR and network analyzer measurements and their design to performance aspects are analyzed in depth. Also HPGCspsila merits and design to electrical factors are discussed in comparison with an Alumina Ceramic and an organic Flip-chip Plastic Ball Grid Array (FCPBGA) packages alongside application space as the three types of packages were built on the same footprints of chip and board IO interfaces for a test site involving different design strategies to accommodate high link density of SerDes links. While HPGC has greater advantage for reliability and high power, and FCPBGA has greater advantage for cost, both demonstrate similar performance in compromising between through transmission and noise isolation parameters. Both HPGC and FCPBGA perform better than Alumina Ceramic in those areas.