Timothy D. Sullivan

Reliability challenges for copper interconnects

Abstract In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low- k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.

Electromigration and stress-induced voiding in fine Al and Al-alloy thin-filmed lines

Physical phenomena underlying failure due to electromigration and stress-induced voiding in fine Al and Al-alloy thin-film conducting lines are examined in the context of accelerated testing methods and structures. Aspects examined include effects due to line isolation (the absence of reservoirs at conductor ends), solute and precipitate phenomena, conductor critical (Blech) length, microstructure, film deposition conditions, and thermal processing subsequent to film deposition. Emphasis is on the isolated, submicron-wide, Al(Cu)-based thin-film interconnection lines of IBM VLSI logic and memory chips.

Stress‐migration related electromigration damage mechanism in passivated, narrow interconnects

In passivated metal interconnects, grain boundary sliding during cooldown from high temperature process steps provides the driving force and sites for void nucleation. Furthermore, residual stresses are known to result in appreciable growth of voids during and after cooldown. The current driven coalescence of such voids is shown to constitute an important failure mechanism for the lines during electromigration testing.

Investigation of via-dominated multi-modal electromigration failure distributions in dual damascene Cu interconnects with a discussion of the statistical implications

Electromigration is a well-known wearout mechanism for metallic interconnects on integrated circuit chips, and has been studied for decades in Al metallization, and for the last several years in Cu metallization. Chip failure is caused by either catastrophic electrical open or by resistance shifts sufficiently large to cause functional failure. The failure mechanism is the creation of a hole or void in the primary conductive layer of the interconnect, caused by a divergence in atomic diffusion in the direction of electron flow. Electromigration results for a 264 sample electromigration study performed on dual damascene copper interconnects are presented and reviewed. The stress results show multi-modal failure distributions and extensive failure analysis provides possible explanations as to the failure modes. Monte Carlo type simulations are used to investigate the statistical implications of using bi-modal fitting to predict reliability performance.

Thermal dependence of voiding in narrow aluminum microelectronic interconnects

A model for the thermal dependence of atomic flux in passivated Al/AlSi very large scale integrated interconnects is presented. The model is derived from stress‐induced alterations in the equilibrium vacancy concentration in the metal, and has an exponential form which can be interpreted as a temperature‐dependent activation energy. The flux model together with the thermal hysteresis of stress reported for thin films can be used to describe a wide range of voiding behavior.

Semiconductor interlevel shorts caused by hillock formation in Al-Cu metallization

A new failure mode in AlCu and AlCuSi metallization is described in which interlevel metal short circuiting occurs between two or more levels of metal. Shorts are caused by theta-phase (Al/sub 2/Cu) hillocks which nucleate and grow during high-temperature vacuum heat treatment and processing, Hillock growth occurs at high-energy sites, such as silicon precipitates and grain boundary nodal points. The growth of Al/sub 2/Cu hillocks depends on the heat-treatment/processing temperature and aluminum film purity. The growth kinetics indicates that grain boundary diffusion is the dominant mass transport mechanism. Methods used to limit theta-phase hillock formation and growth concentrate on the diffusion and nucleation mechanisms involved. Decreasing the heat-treatment/processing temperature slows the atomic diffusion required for hillock growth, and it delays, but does not prevent, theta-phase hillock formation. A 1-h heat treatment (213 Pa, N/sub 2/ ambient) at 350 degrees C produces a high density of large hillocks. Hillock density and height are generally reduced at 300 degrees C. Altering the layered structure of a metallization alters Al/sub 2/Cu hillock growth. Deposition of a hard coating as a cap on the layered structure of an aluminum-based metallization mechanically suppresses hillock formation. A layer of pure aluminum deposited beneath the aluminum-copper layer acts as a sink for copper and delays hillock formation. Increasing film copper content reduces hillock formation: theta-phase hillocks, up to 1.3 mu m in height, are observed in films with 1 wt.% copper, whereas negligible ( >

Thermal conductance of IC interconnects embedded in dielectrics

Accurate prediction of temperatures in metal wiring for integrated circuits is essential to the evaluation of electromigration reliability for high-frequency applications and electrical overload as well as for wafer-level die testing. Accurate prediction requires knowledge of the thermal conductivity of the surrounding dielectric and the heating effect of applied currents. Both quasi-analytical and numerical models for line heating as a function of applied current are presented for the case of lines fully embedded in a dielectric. Heat loss and current density at the melting point are projected as a function of linewidth, line thickness, underlying insulator thickness and insulator thermal conductivity. As intuitively expected, these projections indicate the allowed current density decreases with increasing linewidth, line thickness and insulator thickness, and also decreases as thermal conductivity decreases. Furthermore, the models are found to match heat loss measurements for isolated lines in SiO/sub 2/ and return a value of 1.07 W/m-/spl deg/K for the thermal conductivity of the oxide.

The effects of alloying on stress induced void formation in aluminum‐based metallizations

Evaporated metallizations composed of aluminum alloys and titanium underlayers were patterned, passivated with plasma enhanced chemical vapor deposited SiNx and aged for 1000 h at 150 °C in order to observe stress‐induced void formation. Metal films were analyzed using scanning electron microscopy, transmission electron microscopy, and secondary ion mass spectrometry. The addition of copper to aluminum results in fewer voids than in comparable noncopper metallizations. For Al–Cu films, fewer voids were observed in 1.5 μm lines compared to 5 μm lines, apparently due to the presence of greater stress gradients in the wide line case. Silicon appears to promote void formation by rapid grain boundary diffusion to precipitates. Oxygen incorporation in aluminum produces small grained films, thereby generating many void nucleation sites. High oxygen concentrations produce films with a few long, channel‐like voids and many small voids. Titanium underlayers decrease the percent of metal volume voided for Al and AlS...

Line depletion electromigration characterization of Cu interconnects

Specific details of both fabrication process and geometry of Cu interconnects result in different electromigration (EM) fail modes. This paper discusses EM characteristics of line depletion stress, i.e., for the case of electrons flowing from a via above into a Cu line through a Cu diffusion barrier to cause voiding in the line. For electrons flowing from a W via, for example to a Cu line above, electrical redundancy (i.e., a current shunt layer) exists due to the overlap of line bottom liner over the top of the via, such that a current path still exists in the event that the Cu is removed. When electrons flow from a via above down to a Cu line, the redundancy characteristics can be very different for different via/line layouts, and can result in different EM fail distributions. The solid contact between via above and the liner of the line below can result in tight fail distributions, while weak contact or lack of contact between the via above and the liner of the line below can cause broad (high sigma), or even multimode fail distributions. A few examples and their implications on robust interconnect design are presented. The relation between void size and liner redundancy characteristics is also discussed.

Influence of underlying interlevel dielectric films on extrusion formation in aluminum interconnects

Knowledge of the mechanical properties of interlevel dielectric films and their impact on submicron interconnect reliability is becoming more and more important as critical dimensions in ultralarge scale integrated circuits are scaled down. For example, lateral aluminum (Al) extrusions into spaces between metal lines, which become more of a concern as the pitches shrink, appear to depend partially on properties of SiO2 underlayers. In this article nanoindentation, wafer curvature, and infrared absorbance techniques have been used to study the mechanical properties of several common interlevel dielectric SiO2 films such as undoped silica glass using a silane (SiH4) precursor, undoped silica glass using a tetraethylorthosilicate precursor, phosphosilicate glass deposited by plasma-enhanced chemical vapor deposition and borophosphosilicate glass (BPSG) deposited by subatmosphere chemical vapor deposition. The elastic modulus E and hardness H of the as-deposited and densified SiO2 layers are measured by nanoi...