Byeong Y. Kim

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65/spl mu/m/sup 2/ SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy

Current drive enhancement is demonstrated in sub-40 nm NFETs with strained silicon carbon (Si:C) source and drain using a novel solid-phase epitaxy (SPE) technique for the first time. The very simple process uses no recess etch or epi deposition steps, adds minimal process cost, and can be easily integrated into a standard CMOS process. With a record high 1.65 at% substitutional C concentration in source and drain, 615 MPa uniaxial tensile stress was introduced in the channel, leading to a 35% improvement in electron mobility and 6% and 15% current drive increase in sub-40 and 200 nm channel length devices respectively.

Subwavelength alignment mark signal analysis of advanced memory products

The impact of alignment mark structure, mark geometry, and stepper alignment optical system on mark signal contrast was investigated using computer simulation. Several sub-wavelength poly silicon recessed film stack alignment targets of advanced memory products were studied. Stimulated alignment mark signals for both dark-field and bright-field systems using the rigorous electromagnetic simulation program TEMPEST showed excellent agreement with experimental data. For a dark-field alignment system, the critical parameters affecting signal contrast were found to be mark size and mark recess depth below silicon surface. On the other hand, film stack thickness and mark recess depth below/above silicon surface are the important parameters for a bright-field alignment system. From observed simulation results optimal process parameters are determined. Based on the simulation results some signal enhancement techniques will be discussed.

Ultrafast wafer alignment simulation based on thin film theory

The shrink of semiconductor fabrication ground rule continues to follow Moores law over the past years. However, at the 100 nm node, the fabrication cost starts to rise rapidly. This is mainly due tot he increase of complexity in the fabrication process, including the use of hard masks, planarization, resolution enhancement techniques, etc. Smaller device sizes require higher alignment tolerances. Also, higher degree of complexity makes alignment detection more difficult. For example, planarization techniques may destroy mark topography; hard masks may optically bury alignment marks, and more film layers makes the alignment signal more susceptible to process variations. Therefore in order to achieve reliable alignment, it is absolutely critical to develop an accurate and fast simulation software that can characterize alignment performance based on the film stack structure. In this paper, we will demonstrate that we have built an extremely fast alignment performance based on the film stack structure. In this paper, we will demonstrate that we have built an extremely fast alignment signal simulator for both direct imaging and diffractive detection system based on simple optical theory. We will demonstrate through examples using our advanced DRAM products that it is capable of accurately mapping the multi-dimensional parameter space spanned by various film thickness parameters within a short period of time, which allows both on-the-fly feedback in alignment performance and alignment optimization.

Nitride framed shallow trench isolation (NFSTI) for self-aligned buried strap in high performance trench capacitor DRAM/eDRAM

A self-aligned buried strap process is developed, using nitride frame with oxide hard mask in shallow trench isolation (STI). The connection between cell access transistor and storage node electrode is a key process in trench type DRAM fabrication. Typical trench cell capacitor DRAM technology forms the strap connection under Si substrate (Buried Strap) for better surface planarity. Trench based e-DRAM has significant advantages due to wafer planarity. As the ground rule shrinks beyond 150 nm, the strap resistance variation is critical due to the overlay sensitivity. A new overlay independent strap formation method is introduced, using nitride framed self-aligned trench isolation process which eliminates any possible parasitic connection between the strap and substrate. Masking material and Si RIE process used in NFSTI formation improves array device characteristics. In addition, NFSTI process improves trench level alignment signal contrast due to a phase shift effect.