Gavin Simpson

The use of unpatterned wafer inspection for immersion lithography defectivity studies

The switch from dry to immersion lithography has important consequences regarding wafer defectivity. It has been shown that for successful and efficient defect reductions related to immersion lithography the capability to distinguish immersion/patterning related defects from stack related defects is very useful during process control. These stack related defects can be observed after careful partitioning of individual layer inspections and the analysis of this data through DSA in Klarity. The optimisation of the dark field inspection SP2 tool, central in this paper, shows that improved sensitivity at adequate signal to noise ratio can be obtained on the resist stacks by using the smaller wavelength as the UV-laser light present in the SP2. For bare Si and BARC oblique incidence illumination gives the best sensitivity and captures the most defects. However monitoring of the resist and stacks with resist requires normal incidence illumination since the nature of defects and film result in a higher scattering intensity using normal illumination. The use of an optical filter and a 10% laser power also contributed to establishing a lower and stable background signal for each inspection scan. As immersion tool development is improved and immersion specific defectivity is reduced, the proportion of the stack related defects will become a significant fraction of the overall target for further defect reduction. This includes point defects (embedded particles) or flow defects (streaks) identified and classified using SURFimage. Finally this information is to be used to identify the defect origin(s) for ultimate elimination of defects in the stacks.

The use of high resolution haze for control of SOI surface roughness in a volume production environment.

It is well known that the final surface roughness of SOI wafers has to be controlled to a very tight tolerance in order to maintain transistor parameters required for todays advanced node semiconductor devices. The traditional method for this measurement is to use an atomic force microscope (AFM), but the tools throughput and the area sampled by each measurement are very limited, and AFM repeatability is low. Such measurements can be used during process development, but are not practical during high-volume production.

A proven methodology for detecting photo-resist residue and for qualifying photo-resist material by measuring fluorescence using SP2 bare wafer inspection and SURFmonitor

During the chip making process, complete removal of photo-resist is very critical. Current metrology & analytical methods do not provide enough sensitivity to detect residual amounts of photo-resist remaining on the wafer. Using the novel method described in this study, the Surfscan SP2 and SURFmonitor solution has successfully demonstrated the sensitivity needed to detect residual photo-resist. This method takes advantage of the fact that residual photo-resist, which is organic in nature, will fluoresce. By scanning wafers after the ash and clean step using the SP2 (UV wavelength) unpatterned defect inspection tool equipped with SURFmonitor, it is possible to generate a full-wafer fluorescence SURFimage. This SURFimage was shown to clearly indicate the regions of the wafer where residual photoresist was present.

Study of the Dynamics of Local Particle Removal Efficiencies Using Localized Haze Maps

The local particle removal efficiency (PRE) of nano particles in megasonic cleaning experiments is studied. This approach makes it possible to quantify non uniform cleaning effects over the wafer and to look into the dynamics of particle removal at different areas on the wafer. A direct correlation between PRE and megasonic induced damage of device structures demonstrates that a considerable amount of damage is already formed at less efficiently cleaned areas of the wafer.

Using the low frequency component of the background signal for SiGe and Ge growth monitoring

The objective of this paper is to elucidate novel applications where the low frequency component of a background signal (haze) level of a wafer inspection tool can be used to qualitatively analyze different epitaxial processes. During initial epitaxial development cycles, a fast method of qualifying the growth runs is required. While SEM inspections can sub-sample the wafer, a semi-quantitative way of qualifying growth can be immensely helpful to quicken up the process. In this paper we monitor the epitaxial growth of Ge (heteroepîtaxial) and SiGe strain relaxed buffer layers (SRB approach) with haze.

Progress on background signal analysis of bare wafer inspection systems based on light scattering for III/V epitaxial growth monitoring

The purpose of this paper is to elucidate other applications where the low frequency component of background signal (haze) level of a wafer inspection tool can be used to qualitatively analyze different processes. During initial epitaxial development cycles a fast method of qualifying the growth runs is required. While SEM inspections can sub-sample the wafer, a semi-quantitative way of qualifying growth can be immensely helpful in speeding up the process. In this paper we monitor the epitaxial growth of III/V materials by two different methods: 1) strain relaxed buffers (SRB approach); and, 2) selective epitaxial growth (SEG approach) by using the haze.

Using the Background Signal of a Light Scattering Tool for I/I Photo Resist Strip Optimization and Monitoring

With the continuous decrease of feature size of semiconductor devices new process related challenges must be overcome continuously. One of the key issues for technology development is to have the proper metrology in place to evaluate the myriad process steps fast and accurately. Sometimes the mere existence of a particular metrology is not enough because of cost and throughput issues. The goal of this paper is to show that simply by monitoring the background signal of a light scattering tool, certain process optimizations and monitoring can be done much faster while bringing down the cost significantly. We focus particularly on post I/I strip optimization in this paper.