Sandip Halder

High frequency scanning acoustic microscopy applied to 3D integrated process: Void detection in Through Silicon Vias

Among the technological developments pushed by the emergence of 3D-ICs, Through Silicon Via (TSV) technology has become a standard element in device processing over the past years. As volume increases, defect detection in the overall TSV formation sequence is becoming a major element of focus nowadays. Robust methods for in-line void detection during TSV processing are therefore needed especially for scaled down dimensions. Within this framework, the current contribution describes the successful application of innovative GHz Scanning Acoustic Microscopy (SAM) to TSV void detection in a via-middle approach.

Metrology and inspection for process control during bonding and thinning of stacked wafers for manufacturing 3D SIC's

New challenges for wafer metrology solutions have evolved with 3D-IC manufacturing technology. 3D-IC technology allows stacking single chips, electrically connecting them in the vertical direction, and then forming a chip structure with significant advantages over traditional chips. However, before the 3D-stacking of ICs becomes a mainstream process numerous metrology issues need to be solved. In this paper we discuss the critical in-line metrology needs during bonding and thinning of the device wafers before stacking. We show how TSV depth variations, glue layer defects and grinding issues require monitoring for a successful 3D integration.

Metrology and inspection challenges for manufacturing 3D stacked IC's

In this paper we discuss the numerous metrology and inspection challenges that need to be overcome to really have high volume manufacturing of 3D integrated chips. The key metrology and inspections issues are addressed module wise. We start with the TSV module then move on to the wafer bonding and thinning module. This is followed by the bumping module, de-bonding module and finally we finish with the stacking module. Within each of the modules we show the possible solutions for metrology and inspection and also discuss limitations of the available metrology and inspection if it is warranted.

Detection, binning, and analysis of defects in a GaN-on-Si process for High Brightness Light Emitting Diode's

High Brightness Light Emitting Diodes (HB-LEDs) have received considerable attention during the last few years due to their utilization in numerous consumer products (automotive, displays, etc.). Recently, one of the largest emerging markets for HB-LEDs is the lighting industry because of its lower power requirements and longer lifetime. One of the key limitations for its universal consumer adoption is its higher cost. If the cost for production of an HB-LED is broken up into materials and process steps the price of the sapphire substrate is noticed to be significantly higher than all the individual process and material steps. In such a circumstance the key to making HB-LEDs cheaper is by substrate engineering. Another aspect of the cost is the fact that the traditional sapphire substrates are usually 2 or 4 inches. Therefore, a logical step forward is to move to bigger substrates where yield can be higher. To make this a reality different groups have been working on alternative cheaper and larger substrates (Si/Glass). However, before any technology becomes mature numerous reliability and yield issues need to be fixed. As part of process optimization identifying killer defects is critical. In order to do so we use the Candela platform from KLA Tencor to monitor our epitaxial process. Since, silicon wafers are one of the most common substrates available it obviously emerged as a first choice. We at IMEC have developed a GaN on Si process for making HB-LEDs on 200mm Si (111) substrates. The control of the first epitaxial layers on Si is the key to a successful HB-LED fabrication. Lattice mismatch and thermal coefficient mismatch often lead to wafer bow and defect propagation to the p-GaN surface which can be detrimental to the IQE (Internal Quantum Efficiency). The goal of this work is to understand the different types of defect and the nature of their origin on a typical HB LED stack as well as the detection capability of the tool. Typical defects detected are the cracks/hexagonal defects/pits and particles. Defect data will be analyzed in terms of compressive or tensile stress in the film. This paper focuses on un-optimized EPI wafers in terms of stress/defectivity and crystalline quality to help define the correct inspection thresholds.

In-line metrology and inspection for process control during 3D stacking of IC's

New challenges for wafer metrology solutions have evolved with 3D-IC manufacturing technology. 3D-IC technology allows stacking single chips, electrically connecting them in the vertical direction, and then forming a chip structure with significant advantages over traditional chips. Wafer level 3D integration is a system level architecture in which multiple layers of planar devices are stacked and interconnected through the silicon. The industry is moving past the R&D phase fast. However, before the 3D-stacking of ICs becomes a mainstream process numerous metrology issues need to be solved. In this paper we discuss the critical in-line metrology needs during the manufacture of 3D SICs. We show how TSV depth variations, glue layer defects and grinding issues require monitoring for a successful 3D integration.

Post-dicing particle control for 3D stacked IC integration flows

The concept of 3D integration aims at low cost and high yield processes. For this reason, cleanliness is a concern in process steps such as bonding. However, preceding process steps like dicing and die-level handling are traditionally associated with high levels of contamination. Usually a clean prior to the bonding step will be required. We discuss the requirements of the cleaning process, and explore defect inspection and cryogenic cleaning as viable solutions.

Particle Removal Efficiency and Damage Analysis on Silicon Wafers after Megasonic Cleaning in Solvents

The increasing complexity of semiconductor devices imposes challenging requirements on particle contamination and surface damage. To meet these requirements novel surface-cleaning processes are evaluated, which combine physical energy with organic solvents. In this work, the performance of megasonic cleaning with deionized water (DIW) and N-methylpyrrolidone (NMP) was evaluated in terms of particle removal efficiency (PRE) and damage analysis. The goal was to define an optimum process window where the PRE was maximum and the damage was minimum. Particle removal and damage analysis were performed on unpatterned silicon wafers and with patterned polysilicon lines, respectively, under identical sonic power and process parameters. A comparison between these two solvents reveals that at low sonic power the particle-cleaning performances in DIW and NMP are similar. At high sonic power, in both solvents a detailed analysis of the PRE and damage indicates a non-homogeneous trend over the surface of the wafer. More particularly, in DIW higher PRE and damage are noticed towards the edge of the wafer. In NMP, the opposite trend was observed. However, an equivalent performance was obtained at a lower sonic power in case of NMP compared to DIW. Further understanding of megasonic cleaning in solvents, and an optimization of the process parameters are the key to improve the performance of megasonic cleaning in organic solvents like NMP.

Gan-on-Si process defect detection and analysis for HB-LEDs and power devices

The race to gallium-on-silicon (GaN-on-Si) has been a heated one simply because growth of defect-free GaN-on Si is not an easy problem. The main impetus for this stack comes from a combination of factors, including the ability to use large and cheaper substrates and access to automated back-end manufacturing tools in depreciated IC fabs. Study of the different types of defects during GaN epitaxy is the main goal of this paper. In order to do so, we use scatterrometry is used to analyze different signals. Setting the correct thresholds between signal and noise is key in detecting the defects of interest.

Metrology and inspection rquirements for 3D stacking of ICs

As semiconductor devices become smaller and smaller, to keep up with Moores law, their manufacturing cost increases. Transistors have been continuing to scale and improve in performance. However, the performance improvement gained by scaling is gradually becoming insignificant compared to the negative effects of the interconnect scaling. This had been already predicted by Bohr et al. in 1995. One of the workable ways forward is by reducing the average length of the interconnects. This can be done by forming a new type of vertical interconnect technology that achieves micron scale connections known as TSVs. In order to make this new technology a success several metrology and inspection requirements need to be tackled. In general, the critical 3D processes have been identified to be (i) TSV formation (ii) IC wafer thinning (iii) Debonding and stacking module. In the table below the key challenges within each of the modules have been identified and also the possible solutions for each one of the challenges have been mentioned.

High speed full wafer monitoring of surface, edge and bonding interface for 3Dstacking

3D integration requires innovative process control solutions to ensure the integrity of the device wafers that are bonded, thinned and then de-bonded before permanent bonding. Right now, most 3D-TSV pilot lines use a number of semi-auto or manual inspection tools: Microscopes, interferometers, profilometers and acoustic microscopes. Other sites use automated scanning inspection tools that are not adapted to detect specific 3D integration defectivity. Leading the field, IMEC and Nanda Tech partnered to tailor the Spark platform to the requirements of 3D integration process control. From the pilot line to the high volume manufacturing fabs, Spark provides a flexible process control platform, adapted to handling bonded wafers and finding the defects of interest that will affect expensive customer wafers.