Gawon Kim

Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer

In this paper, we present a lumped element model for coupled interconnect structures of TSV, metal interconnects, and Redistribution Layer (RDL) in Through-Silicon-Via (TSV)-based 3D IC with silicon interposer. We also analyzed the electrical characteristic of coupling between 3D silicon interposer interconnects. The equivalent lumped model is derived and verified with the S-parameter measurement results. The lumped model for TSV, metal, and RDL combined interconnects is verified with the EM solver simulation results. The S-parameter from the proposed model shows good agreement with the result from the measurement and simulation up to 20GHz. We also proposed shielding structures to suppress coupling between silicon interposer interconnects.

Networks-on-chip and Networks-in-Package for High-Performance SoC Platforms

A structured packet-switched networks-on-chip (NoC) is designed and implemented for high-performance heterogeneous SoC design platform. The chip integrates multiprocessors, multiple memories, and other heterogeneous intellectual properties and interconnection with 51mW and 1.6GHz on-chip networks. The NoC adopts a partial activated crossbar, low-energy coding, and low-swing signaling for the power consumption optimization. A network-in-package integrating four NoCs is fabricated in a 676-BGA-type package for larger and scalable systems and demonstrates 2D-image-processing and 3D-graphics applications

Modeling of Eye-Diagram Distortion and Data-Dependent Jitter in Meander Delay Lines on High-Speed Printed Circuit Boards (PCBs) Based on a Time-Domain Even-Mode and Odd-Mode Analysis

Crosstalk induced in a meander delay line produces a significant amount of waveform distortion and data-dependent jitter at the output port. This paper introduces an interpretation of the eye-diagram distortion and the jitter generation mechanism based on a time-domain even- and odd-mode analysis of a coupled transmission line structure. From the proposed analysis, this paper proposes jitter-estimation equations for both the short and long unit line delay cases. The eye-diagram distortion and timing jitter are predicted and estimated, respectively. In order to verify the jitter-estimation equations, a series of microstrip-type printed circuit board test vehicles with the meander delay line are fabricated and tested. The measured jitter shows good agreement with the proposed jitter-estimation equations.

TDR/TDT analysis by crosstalk in single and differential meander delay lines for high speed PCB applications

Meander (serpentine) delay lines are generally used for controlling the skew of the traces in high-speed Printed Circuit Board (PCB) applications. They consist of equal-length unit lines closely packed to each other. However the meander lines deteriorate the total time delay and the waveform distortion in the end of the lines, since each unit line is tightly coupled. In this paper, to predict accurate Time-Domain Reflectometry/Time- Domain Transmit (TDR/TDT) waveforms by crosstalk in the single and differential meander line, simple TDR/TDT equations are proposed in point of the signal integrity. The proposed TDR/TDT waveform equations are verified by using TDR/TDT measurements in the single and differential meander delay lines. Keywords-crosstalk; meander; delay; serpentine; differential line; Time-Domain Reflectometry; TDR; Time-Domain Transmit; TDT

3D strip meander delay line structure for multilayer LTCC-based SiP applications

Recently, the timing control of high-frequency signals is strongly demanded due to the high integration density in three-dimensional (3D) LTCC-based SiP applications. Therefore, to control the skew or timing delay, new 3D delay lines will be proposed. For frailty of the signal via, we adopt the concept of coaxial line and proposed an advanced signal via structure with quasi coaxial ground (QCOX-GND) vias. We will show the simulated results using EM and circuit simulator.

Modeling and Design Optimization of a Wideband Passive Equalizer on PCB Based on Near-End Crosstalk and Reflections for High-Speed Serial Data Transmission

We propose a closed-form analytic model for the newly presented passive equalizer using near-end crosstalk and reflections on printed circuit board (PCB). The proposed model is developed by using impulse response analysis and the Fourier transform. Based on the model, we propose a design-optimization procedure for the passive equalizer, which achieves eye-opening maximization and ISI minimization in order to maximize the equalization performance and reduce the design cycle. In the proposed optimization procedure, the eye-opening is maximized with a parameter sweep and peak distortion analysis, and the ISI is minimized by the proposed negative ISI cancellation technique. The proposed model and the design-optimization procedure are demonstrated experimentally for a data rate of 16 Gb/s on a 40-cm-long backplane PCB, and they achieve wideband equalization with a significant improvement in the voltage and timing margins of the received serial data.

Wideband low power distribution network impedance of high chip density package using 3-D stacked through silicon vias

In this paper, we show the advantages of 3D stacked through silicon via (TSV) in high chip density package in aspect of wideband and low power distribution network (PDN) impedance. We selected large size (80 mum) and large pitch (200 mum) TSV with thick silicon substrate (Si, 80 mum, aspect ratio =1) for on-chip PDN, and compared two total PDN impedances of a PDN with TSVs and a PDN with wire-bondings depending on number of stacked chips from 2 to 10 on a single package. PDN impedance with TSVs includes total capacitance and inductance of TSV and 20 mm times 20 mm package substrate. PDN impedance with wire-bondings shows total capacitance and inductance of wire-bondings and same size package substrate. PDN impedance with TSVs has lower levels with wide bandwidth from 10 MHz to 5 GHz except serial resonance frequency range of the package substrate around 350 MHz. In low frequency range from 10 MHz to 350 MHz, total capacitance of a PDN with TSVs is larger than that of a PDN with wire-bonding because of 0.1 mum thickness silicon oxide (Si02) for blocking DC leakage from TSV to Si substrate. Over 350 MHz, total inductance of a PDN with TSVs is smaller than that of a PDN with wire-bonding because TSV is the smallest electrical path from top surface of stacked chips to the package PDN. The effectiveness of lowering total PDN impedance is better when the number of stacked chips is growing because total length of TSVs is linearly increased with factor 1 while total length of wire-bonding is done with factor radic(2).

Modeling and analysis of die-to-die vertical coupling in 3-D IC

In this paper, die-to-die vertical coupling between clock tree and spiral inductor in three-dimension (3-D) IC is analyzed, and equivalent circuit model for analysis of vertical coupling mechanism is proposed. Analysis and modeling are verified by measurement results of a designed and fabricated test vehicle. The test vehicle has two stacked dies with clock tree or a spiral inductor.

Mode-impedance method for modeling and analysis of crosstalk in differential meander delay lines

In this paper, the timing superposition method and the mode-impedance method have been proposed and verified by the TDR/TDT simulation for crosstalk analysis in differential transmission pairs. The modeled TDR/TDT waveforms in two cases by the mode-impedance method show a good correlation with the original TDR/TDT waveforms.

A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm

Most signals between chips or packages in an electric circuit board require certain delays in order to achieve good timing. An extension of the circuit line that is proportional to the designated time delay has been a usual practice due to cost effectiveness. However, the layout of the line becomes dense due to the small size of packages or circuit boards, and this generates crosstalk, causing signal detection errors. In this paper, a design methodology of delay line layout for crosstalk minimization is developed using the genetic algorithm (GA). The GA requires a large number of function evaluations, and efficient calculation of crosstalk is proposed together with a new technique of generating random line, making offsprings, and mutation. Different optimum results have been obtained for different objectives and compared. Some of the designs were actually manufactured and experimentally tested, showing the validity of the optimum results.