Geert Carchon

Design considerations and technology assessment of phased-array antenna systems with RF MEMS for automotive radar applications

Planar array antennas are attractive for use in future automotive radar systems due to their flexibility in design and control of radar beams. The complexity and cost of a radar front-end phased array can be decreased by applying a beam-steering/switching concept, which reduces the number of parallel RF and baseband signal paths. RF-microelectromechanical systems (MEMS) subsystems are employed because of their excellent RF properties and potential low-cost manufacturability. We present design considerations for prototypical automotive applications of RF-MEMS-based automotive radar front-ends using phased-array antennas based on phase shifters or a Rotman lens. The single RF-MEMS switch is optimized with respect to its RF and thermomechanical behavior taking into account automotive requirements. The respective RF-MEMS subsystems, i.e., phase shifters and single-pole-multiple-throw switching networks are presented in conjunction with packaging and mounting approaches. We evaluate two different wafer-level packaging technologies using glass-frit sealing or polymer sealing. Finally, functional packaged devices are demonstrated: a glass-frit-sealed and flip-chip-mounted RF-MEMS switch and a benzocyclobutene-packaged single-pole-quadruple-throw switch network.

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.

A 9–31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology

A subharmonic down-conversion passive mixer is designed and fabricated in a 90-nm CMOS technology. It utilizes a single active device and operates in the LO source-pumped mode, i.e., the LO signal is applied to the source and the RF signal to the gate. When driven by an LO signal whose frequency is only half of the fundamental mixer, the mixer exhibits a conversion loss as low as 8-11 dB over a wide RF frequency range of 9-31GHz. This performance is superior to the mixer operating in the gate-pumped mode where the mixer shows a conversion loss of 12-15dB over an RF frequency range of 6.5-20 GHz. Moreover, this mixer can also operate with an LO signal whose frequency is only 1/3 of the fundamental one, and achieves a conversion loss of 12-15dB within an RF frequency range of 12-33 GHz. The IF signal is always extracted from the drain via a low-pass filter which supports an IF frequency range from DC to 2 GHz. These results, for the first time, demonstrate the feasibility of implementation of high-frequency wideband subharmonic passive mixers in a low-cost CMOS technology

Optimization of 0-level packaging for RF-MEMS devices

This paper reports on the optimization of the 0-level package for RF-MEMS devices like switches and tunable capacitors. The 0-level package consists of an on-chip cavity obtained by flip-chip mounting a capping chip over the RF-MEMS device, using BCB as the bonding and sealing material. A process for realizing low-profile packages, with caps less than 100 /spl mu/m thick, is described. Coplanar RF feedthroughs are implemented using BCB as the dielectric. It is experimentally shown that a 0-level package using capping chips made of low-loss high-resistivity materials and having a cavity height larger than about 45 /spl mu/m, has a negligible impact on the microwave characteristics of an RF-MEMS device, built on a 50 /spl Omega/ CPW line with ground-to-ground spacing of 150 /spl mu/m.

Thin-film as enabling passive integration technology for RF SoC and SiP

Thin-film Cu/BCB technology with integrated inductors, resistors and capacitors is described for the realization of high-quality on-chip and in-package Si-based passive elements. Thin-film SiP and SoC inductor and transmission line performance is compared. A SiP 7GHz power splitter, a 50GHz BPF, and two 90nm CMOS VCO operating at 5.8GHz and 15GHz with on-chip thin-film inductors are discussed.

Power and noise limitations of active circulators

In this paper, new simple formulas expressing the power and noise limitations for three three-way circulator architectures and three quasi-circulator architectures are derived. It is shown that the power-handling capability of the active three-way circulators is determined by the required transconductance of the transistors in the circuit, while the noise is determined by the drain noise current source. The suitability of the different active circulator architectures for transmit/receive applications is investigated, We conclude that the quasi-circulators based on passive isolation offer the highest performance.

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors

Wafer-level packaging (WLP) technology offers novel opportunities for the realization of high-quality on-chip passives needed in RF front-ends. This paper demonstrates a thin-film WLP technology on top of a 90-nm RF CMOS process with one 15-GHz and two low-power 5-GHz voltage-controlled oscillators (VCOs) using a high-quality WLP or above-IC inductor. The 5-GHz VCOs have a power consumption of 0.33 mW and a phase noise of -115 dBc/Hz and -111 dBc/Hz at 1-MHz offset, respectively, and the 15-GHz VCO has a phase noise of -105 dBc/Hz at 1-MHz offset with a power consumption of 2.76 mW.

24 GHz LNA in 90nm RF-CMOS with high-Q above-IC inductors

K-band RF capabilities of 90nm RF-CMOS combined with thin-film above-IC high-Q inductors is assessed by means of a 24 GHz LNA. The LNA, implemented as a single stage common-source amplifier led to state-of-the art results for CMOS technology at 24 GHz. Record noise figure of 3.2 dB is obtained with a gain of 7.5 dB. Input and output matching are respectively -16 dB and -30 dB. The LNA works with a 1V supply voltage and consumes only 10.6 mA.

A 15 GHz and a 20 GHz low noise amplifier in 90 nm RF-CMOS

The design and measured performance of two low-noise amplifiers at 15 GHz and 20 GHz realized in a 90 nm RF-CMOS process are presented in this work. The 15 GHz LNA achieves a power gain of 12.9 dB, a noise figure of 2.0 dB and an input referred third-order intercept point (IIP3) of -2.3 dBm. The 20 GHz LNA has a power gain of 8.6 dB, a noise figure of 3.0 dB and an IIP3 of 5.6 dBm. Compared to previously reported designs, these two LNAs show lower noise figure at lower power consumption

High-

High-Q inductors are important for the realization of high-performance, low-power RF-circuits. In this paper, on-chip inductors with Q-factors above 40 have been realized above the passivation of a 90-nm RF-CMOS process using wafer-level packaging (WLP) techniques . The influence of a patterned polysilicon and metal ground shield on the inductor-Q is compared and the influence of highly doped active area underneath the inductors is shown. A 5-15 GHz above-IC balun has been realized on 20 Omegamiddotcm silicon with the use of patterned ground shield. The technology is demonstrated by a low-power 90-nm RF-CMOS 5-GHz VCO with a core current consumption of only 150 muA with a 1.2-V supply, and a 10% tuning range with a worst case phase noise of -111 dBc/Hz at 1-MHz offset. A 24-GHz single-stage common-source low-noise amplifier has been realized, with a noise figure of 3.2 dB, a gain of 7.5 dB, and a low power consumption of 10.6 mW