Stefaan Decoutere

High Q inductor add-on module in thick Cu/SiLK/sup TM/ single damascene

Thick Cu single damascene inductors with very high Q factors are integrated on top of a standard aluminum 3LM BEOL process. Obtained Q factors are more than four times higher than Q factors of the inductors of the same geometry processed in the Al 3LM BEOL. For an inductor of 2.8 nH inductance, a Q peak of 24 at 2 GHz was reached by using 4 /spl mu/m thick Cu on a 2 /spl mu/m IMD oxide layer.

Trapping and Reliability Assessment in D-Mode GaN-Based MIS-HEMTs for Power Applications

This paper reports on an extensive analysis of the trapping processes and of the reliability of experimental AlGaN/GaN MIS-HEMTs, grown on silicon substrate. The study is based on combined pulsed characterization, transient investigation, breakdown, and reverse-bias stress tests, and provides the following, relevant, information: 1) the exposure to high gate-drain reverse-bias may result in a recoverable increase in the on-resistance (RON), and in a slight shift in threshold voltage; 2) devices with a longer gate-drain distance show a stronger increase in RON, compared to smaller devices; 3)current transient measurements indicate the existence of one trap level, with activation energy of 1.03 ± 0.09 eV; and 4) we demonstrate that through the improvement of the fabrication process, it is possible to design devices with negligible trapping. Furthermore, the degradation of the samples was studied by means of step-stress experiments in off-state. Results indicate that exposure to moderate-high reverse bias (<; 250 V for LGD = 2 μm) does not induce any measurable degradation, thus confirming the high reliability of the analyzed samples. A permanent degradation is detected only for very high reverse voltages (typically, VDS = 260-265 V, on a device with LGD = 2 μm stressed with VGS = - 8 V) and consists of a rapid increase in gate leakage current, followed by a catastrophic failure. EL measurements and microscopy investigation revealed that degradation occurs close to the gate, in proximity of the sharp edges of the drain contacts, i.e., in a region where the electric field is maximum.

Investigation of PECVD dielectrics for nondispersive metal-insulator-metal capacitors

Metal-insulator-metal (MIM) capacitors with PECVD nitride exhibit trap-induced dispersive behavior, which leads to degradation in capacitor linearity at low frequencies, limiting the accuracy in precision analog circuits. While LPCVD oxide results in nondispersive behavior, the high deposition temperature excludes the use of LPCVD dielectrics for MIM capacitors using the standard back-end metal layers as capacitor bottom plates. The latter is preferred in view of the low substrate coupling needed for RF applications. In this work, alternative PECVD dielectrics have been investigated with respect to frequency dependence of voltage linearity, hysteresis, matching, and leakage characteristics. It will be shown that ONO stacks offer a combination of good voltage linearity, absence of dispersive behavior and hysteresis, excellent matching, and low leakage.

Kinetics of Buffer-Related RON-Increase in GaN-on-Silicon MIS-HEMTs

This letter reports an extensive analysis of the charge capture transients induced by OFF-state bias in double heterostructure AlGaN/GaN MIS- high electron mobility transistor grown on silicon substrate. The exposure to OFF-state bias induces a significant increase in the ON-resistance (Ron) of the devices. Thanks to time-resolved on-the-fly analysis of the trapping kinetics, we demonstrate the following relevant results: 1) Ron-increase is temperature- and field-dependent, hence can significantly limit the dynamic performance of the devices at relatively high-voltage and high temperature (100 °C-140 °C) operative conditions; 2) the comparison between OFF-state and back-gating stress indicates that the major contribution to the Ron-increase is due to the trapping of electrons in the buffer, and not at the surface; 3) the observed exponential kinetics suggests the involvement of point-defects, featuring thermally activated capture cross section; and 4) trapping-rate is correlated with buffer vertical leakage-current and is almost independent to gate-drain length.

Trapping in GaN-based metal-insulator-semiconductor transistors: Role of high drain bias and hot electrons

This paper describes an extensive analysis of the role of off-state and semi-on state bias in inducing the trapping in GaN-based power High Electron Mobility Transistors. The study is based on combined pulsed characterization and on-resistance transient measurements. We demonstrate that—by changing the quiescent bias point from the off-state to the semi-on state—it is possible to separately analyze two relevant trapping mechanisms: (i) the trapping of electrons in the gate-drain access region, activated by the exposure to high drain bias in the off-state; (ii) the trapping of hot-electrons within the AlGaN barrier or the gate insulator, which occurs when the devices are operated in the semi-on state. The dependence of these two mechanisms on the bias conditions and on temperature, and the properties (activation energy and cross section) of the related traps are described in the text.

The Potential of FinFETs for Analog and RF Circuit Applications

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.

Stochastic Matching Properties of FinFETs

For the first time, an experimental assessment of the intradie mismatch properties of a FinFET technology is presented. By applying the analysis to different combinations of gate stack materials, it is shown that the best results are obtained with undoped fins, with matching performances on par or even superior to those of planar MOSFETs. Furthermore, the observation in the narrowest transistors of a noticeable degradation of the mismatch in both the threshold voltage and current factor points to line-edge roughness effects as the presumed key factor influencing intradie mismatch in the smallest fin geometries

On the origin of the two-dimensional electron gas at AlGaN/GaN heterojunctions and its influence on recessed-gate metal-insulator-semiconductor high electron mobility transistors

It is commonly accepted that interface states at the passivation surface of AlGaN/GaN heterostructures play an important role in the formation of the 2DEG density. Several interface state models are cited throughout literature, some with discrete levels, others with different kinds of distributions, or a combination of both. The purpose of this article is to compare the existing interface state models with both direct and indirect measurements of these interface states from literature (e.g., through the hysteresis of transfer characteristics of Metal-Insulator-Semiconductor High Electron Mobility Transistors (MISHEMTs) employing such an interface in the gate region) and Technology Computer Aided Design (TCAD) simulations of 2DEG densities as a function of the AlGaN thickness. The discrepancies between those measurements and TCAD simulations (also those commonly found in literature) are discussed. Then, an alternative model inspired by the Disorder Induced Gap State model for compound semiconductors is proposed. It is shown that defining a deep border trap inside the insulator can solve these discrepancies and that this alternative model can explain the origin of the two dimensional electron gas in combination with a high-quality interface that, by definition, has a low interface state density.

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors

Wafer-level packaging (WLP) technology offers novel opportunities for the realization of high-quality on-chip passives needed in RF front-ends. This paper demonstrates a thin-film WLP technology on top of a 90-nm RF CMOS process with one 15-GHz and two low-power 5-GHz voltage-controlled oscillators (VCOs) using a high-quality WLP or above-IC inductor. The 5-GHz VCOs have a power consumption of 0.33 mW and a phase noise of -115 dBc/Hz and -111 dBc/Hz at 1-MHz offset, respectively, and the 15-GHz VCO has a phase noise of -105 dBc/Hz at 1-MHz offset with a power consumption of 2.76 mW.

Reliability and parasitic issues in GaN-based power HEMTs: a review

Despite the potential of GaN-based power transistors, these devices still suffer from certain parasitic and reliability issues that limit their static and dynamic performance and the maximum switching frequency. The aim of this paper is to review our most recent results on the parasitic mechanisms that affect the performance of GaN-on-Si HEMTs; more specifically, we describe the following relevant processes: (i) trapping of electrons in the buffer, which is induced by off-state operation; (ii) trapping of hot electrons, which is promoted by semi-on state operation; (iii) trapping of electrons in the gate insulator, which is favored by the exposure to positive gate bias. Moreover, we will describe one of the most critical reliability aspects of Metal-Insulator-Semiconductor HEMTs (MIS-HEMTs), namely time-dependent dielectric breakdown.