Geert Janssen

Scalable Sequential Equivalence Checking across Arbitrary Design Transformations

High-end hardware design flows mandate a variety of sequential transformations to address needs such as performance, power, post-silicon debug and test. Industrial demand for robust sequential equivalence checking (SEC) solutions is thus becoming increasingly prevalent. In this paper, we discuss the role of SEC within IBM. We motivate the need for a highly-automated scalable solution, which is robust against a variety of design transformations - including those that alter initialization sequences. This motivation has caused us to embrace the paradigm of SEC with respect to designated initial states. We furthermore describe the diverse set of algorithms comprised within our SEC framework, which we have found necessary for the automated solution of the most complex SEC problems. Finally, we provide several experiments illustrating the necessity of our diverse algorithm flow to efficiently solve difficult SEC problems involving a variety of design transformations.

Exploring power management in multi-core systems

Power dissipation has become a critical design metric in microprocessor-based system design. In a multi-core system, running multiple applications, power and performance can be dynamically traded off using an integrated power management (PM) unit. This PM unit monitors the performance and power of each core and dynamically adjusts the individual voltages and frequencies in order to maximize system performance under a given power budget (usually set by the operating system). This paper presents a performance and power analysis methodology, featuring a simulation model for multi-core systems that can be easily reconfigured for different scenarios and a PM infrastructure for the exploration and analysis of PM algorithms. Two algorithms have been implemented: one for discrete and one for continuous power modes based on non-linear programming. Extensive experiments are reported, illustrating the effect of power management both at the core and the chip level.

Multicore power management: ensuring robustness via early-stage formal verification

Dynamic power management (DPM) is important for multicore architectures. One important challenge for multicore DPM schemes is verifying that they are both safe (cannot lead to power or thermal catastrophes) and efficient (achieve as much performance as possible without exceeding power constraints). The verification difficulty varies among designs, depending, for example, on the particular power management mechanisms utilized and the algorithms used to adjust them. However, verification effort is often not considered in the early stages of DPM scheme design, leading to proposals that can be extremely difficult to verify. To address this problem, we propose using formal verification (with probabilistic model checking) of a high-level, early-stage model of the DPM scheme. Using the model checker, we estimate the required verification effort, providing insight on how certain design parameters impact this effort. Furthermore, we supplement the verifiability results with high-level estimates of power consumption and performance, which allow us to perform a trade-off analysis between power, performance, and verification. We show that this trade-off analysis uncovers design points that are better than those that consider only power and performance.

Performance modeling for early analysis of multi-core systems

Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems, including multiple cores, caches and busses, this problem is compounded by complex performance interactions between cores, caches and interconnections, as well as by tight interdependencies between performance, power and physical characteristics of the design (i.e., floorplan). Although there are many point tools for the analysis of performance, or power, or floorplan of complex systems-on-chip (SoCs), there are surprisingly few works on an integrated tool that is capable of analyzing these various system characteristics simultaneously and allow the user to explore different design configurations and their effect on performance, power, size and thermal aspects. This paper describes an integrated tool for early analysis of performance, power, physical and thermal characteristics of multi-core systems. It includes cycle-accurate, transaction-level SystemC-based performance models of POWER processors and system components (i.e., caches, buses). Power models, for power computation, physical models for floorplanning and packaging models for thermal analysis are also included. The tool allows the user to build different systems by selecting components from a library and connecting them together in a visual environment. Using these models, users can simulate and dynamically analyze the performance, power and thermal aspects of multi-core systems.

A consumer report on BDD packages

BDD packages have matured to a state where they are often considered a commodity. Does this mean that all (publicly and commercially) available packages are equally good? Does this preclude any new developments? In this paper, we present a consumer report on 13 BDD packages and thereby try to answer these questions. We argue that there is a substantial spectrum in quality as measured by various metrics and we found that even the better packages do not always deploy the latest technology. We show how various design decisions underlying the studied packages exhibit themselves at the programming interface level, and we claim that this allows us to predict performance to a certain extent.

Asset health management using predictive and prescriptive analytics for the electric power grid

Electric utilities make up an asset-intensive industry with a broad geographical spread of assets, such as poles, transformers, cables, and switchgear. The utilities face a backlog of aging assets that are pending replacement. Increasingly, a consensus has been reached on moving away from time-based maintenance planning of assets to developing a proactive and smarter asset health management program to meet the competing constraints of reducing customer downtimes, meeting regulatory standards, and managing ever-expanding infrastructure within budget. Incomplete information, fragmented data, and a diversity of asset classes collectively make a holistic assessment of the grid extremely challenging. Working with DTE Energy and Alliander N.V., IBM Research has developed advanced analytics to model asset health and network reliability by predicting the aging of assets, identifying the remaining lifecycle, and computing the network robustness. The analytics exploit data from multiple systems such as enterprise asset management, work management, geographic information systems, supervisory control and data acquisition systems, advanced metering infrastructure, weather systems, and outage management systems. The algorithms systematically evaluate asset health and prioritize preventive, proactive, and corrective maintenance strategies for all asset classes in the electrical network. We describe outcomes, summarizing an overall health score and risk ranking along with a suggested optimal maintenance strategy considering budgetary constraints.

IBM Blue Gene/Q memory subsystem with speculative execution and transactional memory

The memory subsystem of the IBM Blue Gene®/Q Compute chip features multi-versioning and access conflict detection. Its ordered and unordered transaction modes implement both speculative execution (SE) and transactional memory (TM). Blue Gene/Qs large shared second-level cache serves as storage for speculative versions, allowing up to 30 MB of speculative state for the 64 threads of a Blue Gene/Q node, which in the extreme can be associated with a single large transaction. Using the shared access to speculative data, the SE model implements forwarding, allowing data produced by one thread to be accessed by another thread while both are still speculative. This paper presents an overview of Blue Gene/Qs approach to TM and SE: the memory subsystem hardware and operating system extensions, IBM XL compiler support via OpenMP® extensions, and a cost estimation model for executing code speculatively. The model is validated using synthetic benchmarks.

First cadathlon programming contest held at 2002 ICCAD

IN THE SPIRIT OF the long-running ACM programming contest, the Special Interest Group on Design Automation (SIGDA) organized an EDA programming contest, the CADathlon. SIGDA held the CADathlon on 10 November 2002, at the Double Tree Hotel in San Jose, Calif., as part of the Sunday program for the International Conference on Computer-Aided Design (ICCAD). Students, working in teams of two, competed to solve six problems from different CAD areas. The CADathlon challenged students in their CAD knowledge, and in their problemsolving, programming, and teamworking skills. The contest provided a platform for academia and industry to focus attention on the best and brightest of next-generation CAD professionals. The CADathlon is an innovative initiative that assists in attracting top students to the EDA field. The students and selection process The CADathlon competition was open to all graduate students specializing in CAD who were currently enrolled full-time at a PhD-granting institution in any country. Each student team submitted an online application. Students provided information about their academic and course backgrounds, and described their three most challenging EDA programming experiences. Thirty teams applied for the CADathlon, including six non-US teams from Taiwan and Brazil. Organizers ranked students based on their EDA programming experiences, giving preference to more senior students. SIGDA invited 20 teams to participate in the contest, of which 13 received full awards to cover their travel and lodging. Awards went to the most qualified students. Of the 20 teams invited, 15 accepted invitations. SIGDA also gave all participants free ICCAD registration to encourage them to attend the conference and network with the EDA community. Biographies of all participants are available on the CADathlon Web site: http://www. sigda.org/programs/cadathlon.