Gen Fujita

Spatiotemporal segmentation for compact video representation

In this paper, a novel hierarchical object-oriented video segmentation and representation algorithm is proposed. The local variance contrast and the frame difference contrast are jointly exploited for structural spatiotemporal video segmentation because these two visual features can indicate the spatial homogeneity of the grey levels and the temporal coherence of the motion fields efficiently, where the two-dimensional (2D) spatiotemporal entropic technique is further selected for generating the 2D thresholding vectors adaptively according to the variations of the video components. After the region growing and edge simplification procedures, the accurate boundaries among the different video components are further exploited by an intra-block edge extraction procedure. Moreover, the relationships of the video components among frames are exploited by a temporal tracking procedure. This proposed object-oriented spatiotemporal video segmentation algorithm may be useful for MPEG-4 system generating the video object plane (VOP) automatically.

A new motion estimation core dedicated to H.263 video coding

A VLSI architecture of a motion estimator is described for the H.263 low bitrate video coding. Adopting an efficient hierarchical search algorithm, a new motion estimator yields high quality vectors with small area occupancy and at a low operation frequency. A one-dimensional Processing Element array is devised to be tuned to the H.263 encoding, which treats both the advanced prediction mode and the PB-frame mode. The proposed motion estimation core is integrated in 1.34 mm/sup 2/ by using 0.35 /spl mu/m CMOS 3LM technology, which operates at 15 MHz, and hence enables the realtime motion estimation of QCIF pictures.

Automatic moving object extraction toward compact video representation

An automatic object-oriented video segmentation and representation algorithm is proposed, where the local variance contrast and the frame difference contrast are jointly exploited for meaningful moving object extraction because these two visual features can indicate the spatial homogeneity of the gray levels and the temporal coherence of the motion fields efficiently. The 2-D entropic thresholding technique and the watershed transformation method are further developed to determine the global feature thresholds adaptively according to the variation of the video components. The obtained video components are first represented by a group of 4x4 blocks coarsely, and then the meaningful moving objects are generated by an iterative region-merging procedure according to the spatiotemporal similarity measure. The temporal tracking procedure is further proposed to obtain more semantic moving objects and to establish the correspondence of the moving objects among frames. Therefore, the proposed automatic moving object extraction algorithm can detect the appearance of new objects as well as the disappearance of existing objects efficiently because the correspondence of the video objects among frames is also established. Moreover, an object-oriented video representation and indexing approach is suggested, where both the operation of the camera (i.e., change of the viewpoint) and the birth or death of the individual objects are exploited to detect the breakpoints of the video data and to select the key frames adaptively.

Architecture of embedded zerotree wavelet based real-time video coder

A VLSI architecture of a real-time wavelet video coder is described, with the main focus put on the efficient VLSI implementation and scalable code generation. To achieve this goal, this architecture devises a modified 2-D sub-band decomposition scheme in conjunction with a parallelized block-based EZW (Embedded Zerotree Wavelet) coding. Experimental results are also shown in comparison with MPEG2 so as to demonstrate the viability of the proposed architecture.

Low-power implementation of H.324 audiovisual codec dedicated to mobile computing

A VLSI implementation of the H.324 audiovisual codec is described. A number of sophisticated low-power architectures have been devised dedicatedly for the mobile use. A set of specific functional units, each corresponding to a process of H.263 video codec, is employed to lighten different performance bottlenecks. A compact DSP core composed of two MAC units is used for both ACELP and MP-MLQ coding schemes of the G.723.1 speech codec. The proposed audiovisual codec core has been implemented by using 0.35 /spl mu/m CMOS 4LM technology, which contains totally 420 K transistors with the dissipation of 224.32 mW from single 3.3 V supply.

Realtime wavelet video coder based on reduced memory accessing

In this paper, the VLSI implementation of a real-time EZW video coder is presented. The proposed architecture adopts a modified 2-D DWT subband decomposition scheme, with the purpose of reducing the transposition memory requirements of 2-D DWT. In addition, through the use of a parallelized partial zerotree EZW scheme, temporary buffer requirements between the DWT and EZW modules are also reduced. The video encoder is integrated in a 0.35 um 3LM chip by using 341 K transistors on a 4.93 x 4.93 mm2 die.

A wireless data system constructed of SAW-based receiver/transmitter and its applications to medical cares

The present paper describes a wireless data system dedicated to medical cares by employing SAW-based receiver and transmitter. In order to realize the portability as well as to lower the power consumption, an ASIC architecture is additionally devised to implement the intermittent drive and the communication protocol, by means of which the wireless data system can admit portable monitoring facilities in medical cares, i.e. the wandering prevention of patients with senile dementia and the 24-hour observation of portable electrocardiographs.

Hierarchical object-oriented image and video segmentation algorithm based on 2D entropic thresholding

In this paper, a novel object-oriented hierarchical image and video segmentation algorithm is proposed based on 2D entropic thresholding, where the local variance contrast is selected for generating the 2D entropic surface because this parameter can indicate the strength of the edge accurately. The extracted object is first represented by a group of (4 X 4) blocks coarsely, then the intra-block edge extraction procedure and the joint spatiotemporal similarity test among neighboring blocks are further performed for determining the meaningful real objects. Experimental results have confirmed that the proposed hierarchical algorithm may be very useful for MPEG-4 applications, such as determining the Video Object Plane Formation automatically and selecting the coding pattern adaptively. A novel fast algorithm is also introduced for reducing the search burden. Moreover, this unsupervised algorithm also makes the automatic image and video segmentation possible.

Low-power H.263 video CoDec dedicated to mobile computing

A low-power H.263 video codec core dedicated to low bitrate visual communication is described. A number of sophisticated architectures have been devised by attempting not only to minimize the total chip area but also to reduce the power consumption to such an extent that the operation frequency can be slowed down to 15 MHz. As a result, the whole encoding and decoding facilities of an H.263 video codec core have been integrated in the die area of 6.54 mm/sup 2/ by means of a 0.35 /spl mu/m CMOS technology, with the dissipation of 146.60 mW from a single 3.3 V supply.

VLSI implementation of a realtime wavelet video coder

The architecture of a realtime wavelet video coder is described, with the main emphasis put on memory bandwidth reduction and efficient VLSI implementation. The proposed architecture adopts a modified 2-D subband decomposition scheme, alongside of a parallelized pipelined Embedded Zerotree Wavelet coder architecture. The video encoder is integrated in a 0.35 /spl mu/m 3LM chip by using 341 K transistors on a 4.93/spl times/4.93 mm/sup 2/ die, which can process 720/spl times/480 30 fps pictures in realtime.