K. Matsumura

A wireless data system constructed of SAW-based receiver/transmitter and its applications to medical cares

The present paper describes a wireless data system dedicated to medical cares by employing SAW-based receiver and transmitter. In order to realize the portability as well as to lower the power consumption, an ASIC architecture is additionally devised to implement the intermittent drive and the communication protocol, by means of which the wireless data system can admit portable monitoring facilities in medical cares, i.e. the wandering prevention of patients with senile dementia and the 24-hour observation of portable electrocardiographs.

Architecture for MPEG2 MP@HL real time motion estimator

A VLSI architecture of a motion estimator is proposed, dedicated to MPEG2 MP@HL, which adopts a two-level hierarchical searching algorithm in detecting motion vectors. A novel mechanism is introduced into the full-search procedure which attempts the maximum possible reuse of reference pixels to reduce the bandwidth of frame memory interface. The proposed architecture has been integrated into a 0.6 /spl mu/m triple-metal CMOS chip which contains 1200 K transistors on a 12.2/spl times/12.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL.

Protocol module of wireless data system dedicated to medical care

A wireless data system is constructed with the use of a SAW-based transmitter and receiver, have been conceived specifically for short range RF link applications. In order to realize the portability as well as to reduce the power consumption, an ASIC architecture is devised to be incorporated with the transmitter/receiver so as to implement the intermittent drive and communication protocol mechanism. By means of a sophisticated drive and protocol mechanism, the wireless data system is applied to the monitoring facilities in medical care. The ASIC module has been implemented by employing 0.6 /spl mu/m three-metal-layer CMOS process. The power dissipation has been lowered to 0.98 mW at 3 V.

Matrix-vector multiplier module for natural/synthetic hybrid video coding

An architecture of a Matrix-Vector Multiplier (MVM) is devised, which is dedicated to MPEG-4 natural/synthetic video decoding. The MVM can perform the matrix-vector multiplication both in the IDCT (Inverse Discrete Cosine Transform) and in the geometrical transformation of 3D CG; or specifically, can achieve the multiplication of a 4/spl times/4-matrix by a 4-tuple vector necessary both in the 1D IDCT for eight pixels and in the geometrical transformation for a point in a 3D space. The present paper describes a new architecture of this MVM, and also shows the implementation result of a functional module composed of four MVMs with the use of 440 K transistors, which can operate at 20 MHz or less.

Implementation of half-pel precision motion estimator for MPEG2 MP@HL

A half-pel precision single chip motion estimator is described dedicatedly for MPEG2 MP@HL moving pictures. Adopting a two-level hierarchical searching algorithm and the maximum possible reuse mechanism of reference pixels, MP@HL motion estimation is successfully facilitated. The broadcasting type PE array is used both for integer-pel precision vector and half-pel precision vector search processes. The proposed motion estimator is integrated in a 0.6 /spl mu/m triple-metal CMOS chip, which contains 1450 K transistors on a 12.7/spl times/13.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables real time motion estimation for MPEG2 MP@HL.

VLSI implementation of hierarchical motion estimator for MPEG2 MP@HL

A VLSI motion estimator dedicated to MPEG2 MP@HL has been developed. Adopting a two-level hierarchical searching algorithm in detecting motion vectors, the computational labor can be reduced by 1/70 in comparison with the conventional algorithm. The proposed motion estimator is integrated in a 0.6 /spl mu/m triple-metal CMOS chip which contains 1,200 K transistors on a 12.2/spl times/12.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL.