Morgan Hirosuke Miki

Low-power implementation of H.324 audiovisual codec dedicated to mobile computing

A VLSI implementation of the H.324 audiovisual codec is described. A number of sophisticated low-power architectures have been devised dedicatedly for the mobile use. A set of specific functional units, each corresponding to a process of H.263 video codec, is employed to lighten different performance bottlenecks. A compact DSP core composed of two MAC units is used for both ACELP and MP-MLQ coding schemes of the G.723.1 speech codec. The proposed audiovisual codec core has been implemented by using 0.35 /spl mu/m CMOS 4LM technology, which contains totally 420 K transistors with the dissipation of 224.32 mW from single 3.3 V supply.

Realtime wavelet video coder based on reduced memory accessing

In this paper, the VLSI implementation of a real-time EZW video coder is presented. The proposed architecture adopts a modified 2-D DWT subband decomposition scheme, with the purpose of reducing the transposition memory requirements of 2-D DWT. In addition, through the use of a parallelized partial zerotree EZW scheme, temporary buffer requirements between the DWT and EZW modules are also reduced. The video encoder is integrated in a 0.35 um 3LM chip by using 341 K transistors on a 4.93 x 4.93 mm2 die.

A low-power DSP core architecture for low bitrate speech codec

A VLSI implementation of a low-power DSP is described, which is dedicated to the G.723.1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The proposed DSP architecture has been integrated in a total area of 7.75 mm/sup 2/ by using a 0.35 /spl mu/m CMOS technology, which can operate at 10 MHz with the dissipation of 45 mW from a single 3 V supply.

Low-power H.263 video CoDec dedicated to mobile computing

A low-power H.263 video codec core dedicated to low bitrate visual communication is described. A number of sophisticated architectures have been devised by attempting not only to minimize the total chip area but also to reduce the power consumption to such an extent that the operation frequency can be slowed down to 15 MHz. As a result, the whole encoding and decoding facilities of an H.263 video codec core have been integrated in the die area of 6.54 mm/sup 2/ by means of a 0.35 /spl mu/m CMOS technology, with the dissipation of 146.60 mW from a single 3.3 V supply.

Evaluation of processor code efficiency for embedded systems

This paper evaluates the code efficiency of the ARM, Java, and x86 instruction sets by compiling the SPEC CPU95/ CPU2000/JVM98 and CaffeineMark benchmarks, in terms of code sizes, basic block sizes, instruction distributions, and average instruction lengths. As a result, mainly because (i) the Java architecture is a stack machine, (ii) there are only four local variables which can be accessed by a 1-byte instruction, and (iii) additional instructions are provided for the network security, the code efficiency of Java turns out to be inferior to that of ARM Thumb. Moreover, through this efficiency analysis it should be claimed that a more efficient code architecture can be constructed by taking minute account of the customization of an instruction set as well as the number of registers.

VLSI implementation of a realtime wavelet video coder

The architecture of a realtime wavelet video coder is described, with the main emphasis put on memory bandwidth reduction and efficient VLSI implementation. The proposed architecture adopts a modified 2-D subband decomposition scheme, alongside of a parallelized pipelined Embedded Zerotree Wavelet coder architecture. The video encoder is integrated in a 0.35 /spl mu/m 3LM chip by using 341 K transistors on a 4.93/spl times/4.93 mm/sup 2/ die, which can process 720/spl times/480 30 fps pictures in realtime.

Recursive maximum likelihood decoder for high-speed satellite communication

A decoder of (64,35) Reed-Muller subcode has been implemented, dedicatedly for high-speed satellite communication. The trellis-based recursive maximum likelihood decoding algorithm, which greatly reduces the computational costs of the conventional Viterbi algorithm, can be performed on a single chip by using 3-stage pipeline architecture of an add-compare-select (ACS) tree. By using 0.6 /spl mu/m CMOS triple-metal technology, the (64,35) decoder integrates totally 160,023 gates into a 151.3 mm/sup 2/ die and operates at 60 MHz. The 600 Mbps (64,40) decoding system required for satellite communication can be constructed by employing 32 proposed decoders in parallel.

A Low-Power H.263 Video CoDec Core Dedicated to Mobile Computing

A number of novel VLSI architectures are devised for an H.263 video codec core in terms of low bitrate visual communication. The potential of the practicability for mobile computing has been extremely explored by attempting not only to minimize the total chip area but also to reduce the power consumption to such an extent that the operation frequency can be slowed down to 15MHz. The whole encoding and decoding facilities have been integrated in the die area of 7.66 mm 2 by means of a 0.35m CMOS technology, with the dissipation of 146.60 mW from a single 3.3V supply.

High Performance Java Hardware Engine and Software Kernel for Embedded Systems

This paper describes an effective approach to Java execution through the use of embedded processors. A pair of hardware engine and software kernel are devised for existing embedded systems in order to execute Java applications efficiently, in such a way that 39 instructions are added to the original JVM dedicatedly for the software kernel implementation. The whole embedded system including the hardware engine of 6-stage pipeline with 30K gates can be integrated in a single chip. The proposed approach improves the execution speed by a factor of 5.7 in comparison with J2ME software implementation.