Gen Pei

Metal nanocrystal memories. I. Device design and fabrication

This paper describes the design principles and fabrication process of metal nanocrystal memories. The advantages of metal nanocrystals over their semiconductor counterparts include higher density of states, stronger coupling with the channel, better size scalability, and the design freedom of engineering the work functions to optimize device characteristics. One-dimensional (1-D) analyses are provided to illustrate the concept of work function engineering, both in direct-tunneling and F-N-tunneling regimes. A self-assembled nanocrystal formation process by rapid thermal annealing of ultrathin metal film deposited on top of gate oxide is developed and integrated with NMOSFET to fabricate such devices.

FinFET design considerations based on 3-D simulation and analytical modeling

Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplaces equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.

Metal nanocrystal memories-part II: electrical characteristics

This paper describes the electrical characteristics of the metal nanocrystal memory devices continued from the previous paper [see ibid., vol. 49, p. 1606-13, Sept. 2002]. Devices with Au, Ag, and Pt nanocrystals working in the F-N tunneling regime have been investigated and compared with Si nanocrystal memory devices. With hot-carrier injection such as the programming mechanism, retention time up to 10/sup 6/ s has been observed and 2-bit-per-cell storage capability has been demonstrated and analyzed. The concern of the possible metal contamination is also addressed by current-voltage (I-V) and capacitance-voltage (C-V) characterizations. The extracted inversion layer mobility and minority carrier lifetime suggest that the substrate is free from metal contamination with continuous operations.

A physical compact model of DG MOSFET for mixed-signal circuit applications- part I: model description

To use double-gate (DG) MOSFET for mixed-signal circuit applications, especially for circuits in which the two gates are independently driven, such as in the case of dynamic-threshold and fixed-potential-plane operations, physical compact models that are valid for all modes of operations are necessary for accurate design and analysis. Employing physically rigorous current-voltage (I-V) relationship in subthreshold and above-threshold regions as asymptotic cases, we have constructed a model that joins the two operating regions by using carrier-screening functions. We have included consistently source/drain series resistance, low drain-field mobility, and small-geometry effects of drain-induced barrier lowering (DIBL), MOS interface mobility, velocity saturation and channel-length modulation (CLM) with validation from two-dimensional (2-D) distributed simulation. All model parameters can be extracted from large-signal I-V characteristics in dc conditions with given geometrical data. Parameter extraction methods and verification from simulation are presented in Part II.

Pulsed wave interconnect

Pulsed wave interconnect is proposed for global interconnect applications. Signals are represented by localized wave-packets that propagate along the interconnect lines at the local speed of light to trigger the receivers. Energy consumption is reduced through charging up only part of the interconnect lines and using the voltage doubling property of the receiver gate capacitances. In a 0.18-/spl mu/m CMOS technology case study, SPICE simulations show that pulsed wave interconnect can save up to 50% of energy and /spl sim/30% of chip area in comparison with the repeater insertion method. A proposed signal splitting structure provides reasonable isolations between different receivers. Measured S-parameters of 3.8-mm interconnect lines fabricated through CMOS foundry showed that the distortion and attenuation of a pico second signal are much less serious than the theoretical predictions. Pulsed wave interconnect also enables time division application of a single line to boost its bit rate capacity. The use of nonlinear transmission lines (NLTL) is also proposed to overcome pulse broadening and attenuation caused by dispersion and frequency-dependent losses. Pulsed waves on an NLTL may be generated, transmitted, split and detected with components realizable in bulk and SOI CMOS technologies. Tapered NLTL can be used for pulse compression. NLTL edge sharpening abilities may be applicable for signal rise time control.

Independently driven DG MOSFETs for mixed-signal circuits: part I-quasi-static and nonquasi-static channel coupling

The two tightly coupled channels in independently driven double-gate (IDDG) MOSFET offer new opportunities in constructing mixed-signal circuit modules. Understanding of channel coupling in various bias and frequency regimes is imperative to conceptualize the circuit design and optimization. In Part I, we will investigate both quasi-static and nonquasi-static channel coupling in IDDG through capacitance simulation. The charge reshuffling between channels provides effective coupling at high frequency when source/drain (S/D) carriers cannot respond spontaneously to the applied gate signals, which opens up new high-frequency circuit possibilities beyond the S/D transit time set by the lithography limit. The bias and frequency regions that enhance channel coupling are identified. The transition frequency related to channel charge reshuffling is investigated for its dependence on device geometry. Operational principles and practical limitations are discussed. In Part II, we will present the circuit design examples based on the interchannel coupling.

A physical compact model of DG MOSFET for mixed-signal circuit applications - part II: Parameter extraction

For pt. see ibid., vol. 50, no. 10, p. 2135 (2003). Based on the physical double-gate MOSFET model described in Part I, we present a systematic parameter extraction methodology that avoids parameter interdependence between different physical effects whenever possible. Several extraction schemes are compared for precise modeling of small-signal and large-signal characteristics. The physical model and the extraction methodology are verified through the reproduction of the simulated drain current, incremental drain resistance, and transconductance per unit current, which are parameters of particular interest to mixed-signal circuit designs.

A novel quad source/drain metal nanocrystal memory device for multibit-per-cell storage

Based on the 2-bit-per-cell metal nanocrystal memories, a novel quad source/drain device capable of 4 bits per cell data storage is demonstrated. Along with the new device structure, a reliable parallel read scheme with low V/sub DS/ is also proposed and verified for 4-bit-per-cell operations. The proposed read scheme requires 1.125 read operations on average to read out the 4 bits stored in a cell, while minimizing the read disturb and interference between the different storage bits.

Independently driven DG MOSFETs for mixed-signal circuits: part II-applications on cross-coupled feedback and harmonics generation

Circuit applications utilizing the tight quasi-static and nonquasi-static channel coupling in independently driven double-gate (IDDG) MOSFETs are presented. The performances of cross-coupled differential amplifiers and mixers with IDDG are compared with those of the SDDG counterparts. The quasi-static coupling in IDDG increases output voltage swing and improves voltage waveform symmetry in the cross-coupled differential amplifier. The nonquasi-static coupling in IDDG provides fast feedback in the differential amplifiers, and allows higher frequencies in the input signals for harmonic generation in mixers. We have identified plausible advantages in IDDG that cannot be readily implemented by SDDG, which justifies the fabrication cost and parasitic capacitance penalty of IDDG.

Band-to-Band Tunneling by Monte Carlo Simulation for Prediction of MOSFET Gate-Induced Drain Leakage Current

Gate induced drain leakage (GIDL) current caused by band-to-band tunneling is studied by Monte Carlo simulation with ballistic least-action trajectory integration. Together with weak inversion and early subthreshold simulation by drift-diffusion formalism, the entire range of the OFF-state drain current can be predicted for technology evaluation. The methodology is demonstrated by a case study for source/drain asymmetry super-halo design.