Venkat Narayanan

Metal nanocrystal memories. I. Device design and fabrication

This paper describes the design principles and fabrication process of metal nanocrystal memories. The advantages of metal nanocrystals over their semiconductor counterparts include higher density of states, stronger coupling with the channel, better size scalability, and the design freedom of engineering the work functions to optimize device characteristics. One-dimensional (1-D) analyses are provided to illustrate the concept of work function engineering, both in direct-tunneling and F-N-tunneling regimes. A self-assembled nanocrystal formation process by rapid thermal annealing of ultrathin metal film deposited on top of gate oxide is developed and integrated with NMOSFET to fabricate such devices.

Metal nanocrystal memories-part II: electrical characteristics

This paper describes the electrical characteristics of the metal nanocrystal memory devices continued from the previous paper [see ibid., vol. 49, p. 1606-13, Sept. 2002]. Devices with Au, Ag, and Pt nanocrystals working in the F-N tunneling regime have been investigated and compared with Si nanocrystal memory devices. With hot-carrier injection such as the programming mechanism, retention time up to 10/sup 6/ s has been observed and 2-bit-per-cell storage capability has been demonstrated and analyzed. The concern of the possible metal contamination is also addressed by current-voltage (I-V) and capacitance-voltage (C-V) characterizations. The extracted inversion layer mobility and minority carrier lifetime suggest that the substrate is free from metal contamination with continuous operations.

Design Optimization of Metal Nanocrystal Memory—Part I: Nanocrystal Array Engineering

The three-dimensional (3D) electrostatics together with the modified Wentzel-Kramers-Brillouin tunneling model has been implemented to simulate the programming and retention characteristics of the metal nanocrystal (NC) memories. Good agreements with experimental data are first demonstrated to calibrate the transport parameters. In contrast to previous works, the 3D electrostatic effects investigated in this paper are proven very significant in the memory operations. Therefore, new design criteria of metal NC memories are investigated. Part I presents the physical model and the NC array design optimization. A sparse and large-size NC array, which is suitable for the one-dimensional narrow-channel memories, provides higher program/erase tunneling current density due to the field-enhancement effect and lower charging energy due to the large NC capacitance. On the other hand, to achieve a sufficient memory window, fast programming speed, and long retention time in the typical two-dimensional channel memories, a dense and large-size NC array is favorable while taking the tradeoff with the NC number density into account. Based on the same theoretical model, the authors continue in Part II to consider the design optimization when high-K dielectrics can be employed

Asymmetric electric field enhancement in nanocrystal memories

The electrostatic model for nanocrystal memories is used to illustrate the fundamental difference of the metal nanocrystal memory in low-voltage program/erase (P/E) operations in comparison with semiconductor nanocrystal and trap-based memories. Due to repulsion of potential contours inside conductors, the metal nanocrystals will significantly enhance the electric field between the nanocrystal and the sensing channel set up by the control gate bias and, hence, can achieve much higher efficiency in low-voltage P/E. On the other hand, the electric field originated from the stored charge will only be slightly different for metal and semiconductor nanocrystal cases. We presented the electrostatic models by both approximate analytical formulation and three-dimensional numerical simulation in a nanocrystal array. Operations of P/E and read disturbance were analyzed for the cases of homogeneous charge distribution, silicon, and metal nanocrystals. In the P/E condition of +5/-5 V, the metal nanocrystal memory offers around 1.6 times higher peak fields than Si counterparts and almost three times higher than that from the one-dimensional model for homogeneous charge distribution. The field enhancement factor suggests the design criteria of oxide thickness, nanocrystal size, and spacing. The advantage of asymmetric field enhancement of metal nanocrystals will be even more prominent when high-K gate dielectrics are employed.

Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering

Based on the physical model of nanocrystal (NC) memories described in Part I, a systematic investigation of gate-stack engineering is presented, including high-K control and tunneling oxides. The high-K control oxide enables the effective-oxide-thickness scaling without compromising the memory performance, owing to the low charging energy and large channel-control factor from the three-dimensional electrostatics. The high-K tunneling oxide, on the other hand, improves the retention characteristics utilizing the asymmetric tunneling barrier more effectively away from the direct tunneling regime. Finally, with the optimization strategies introduced in both parts I and II, a metal NC memory design with 1.0-V memory window, 13-mus programming, 2.5-mus erasing, and over 10-year retention time has been demonstrated at plusmn4V operation, which highlights the potential of NC memories as the next-generation nonvolatile memory

A novel quad source/drain metal nanocrystal memory device for multibit-per-cell storage

Based on the 2-bit-per-cell metal nanocrystal memories, a novel quad source/drain device capable of 4 bits per cell data storage is demonstrated. Along with the new device structure, a reliable parallel read scheme with low V/sub DS/ is also proposed and verified for 4-bit-per-cell operations. The proposed read scheme requires 1.125 read operations on average to read out the 4 bits stored in a cell, while minimizing the read disturb and interference between the different storage bits.

Reduction of metal-semiconductor contact resistance by embedded nanocrystals

By utilizing the enhanced electric fields from self-assembled metal nanocrystals embedded in another metal with a different work function, we demonstrate a novel scheme to significantly enhance the tunneling current through a metal/semiconductor interface. Improvement in contact resistance by more than 100 times has been demonstrated for cases originally limited by the interface doping concentration or the annealing thermal budget. This new technique offers an additional process option to source/drain contacts, especially for low-temperature TFTs and Schottky-barrier MOSFETs.

3D analytical subthreshold and quantum mechanical analyses of double-gate MOSFET

Scaling studies on double-gate MOSFET and its variations are critical to CMOS technology node below 70 nm. In this work we present 3D analytical modeling in the subthreshold region and analytical quantum mechanical considerations of channel coupling that can facilitate device design and technology selection. The analytical models are corroborated with both experiments and distributed simulation.

Low programming voltages and long retention time in metal nanocrystal EEPROM devices

Conventional Si/Ge nanocrystal EEPROM devices have several advantages over conventional EEPROM with continuous floating gate. However, to maintain good retention characteristics the programming voltages (write and erase) cannot be scaled down easily. Interface and dopant fluctuations at the Si/Ge nanocrystal interface also cause device design difficulty. We demonstrate for the first time that metal nanocrystal EEPROMs can have much lower programming voltages by careful choice of the metal floating-gate workfunction. The interface fluctuations are at a minimum due to the metal density of states. The retention characteristic for metal nanocrystals is similar to that of Si nanocrystals in view of the Coulomb blockade. Process integration of the metal floating gate on thin tunneling oxide is greatly improved by the self-assembly step of nanocrystal formation. Energy minimization during self assembly will relax the interface stress and stabilize the metal structure to avoid penetration and contamination. Together with Schottky contact injection improvement, the introduction of metal nanocrystals can push deep submicron CMOS and EEPROM scaling for more technology generations.

Three-dimensional analytical modeling of nanocrystal memory electrostatics

The integration of a two-dimensional distribution of discrete nanoscale floating gates in the nonvolatile memory gate stack produces significant three-dimensional (3D) electrostatic effects in contrast to the conventional flash memory modeling where a one-dimensional (1D) treatment is often sufficient. We have developed an analytical model for 3D electrostatics, which can not only enhance design intuition for device optimization but also provide convenient integration with a Schrodinger solver for self-consistent transport calculations since it is independent of discretization requirements. The model is validated by comparing with a finite-element Maxwell equation solver. The 3D analytical model has a much lower root-mean-square error than the 1D formulation for electrostatic potentials and fields in the tunneling path.