Georg Roehrer

Investigations on an Isolated Lateral High-Voltage n-channel LDMOS Transistor with a Typical Breakdown of 150V

This work describes a concept of an isolated high-voltage (HV) n-channel LDMOS transistor, which can be used as a high-side switch instead of a HV PMOS transistor. HV n-channel LDMOSFETs for 120V applications (blocking voltage over 150V) were used in the study. The devices were fabricated in a 0.35 mum CMOS-based HV technology. Hot carrier stress experiments (under gate voltage VGS = 10V and drain voltage VD = 120V) were performed for device reliability evaluations. The devices with non-uniformly optimized n-well show an excellent trade-off between blocking voltage (BV) and on-resistance while keeping hot carrier induced degradation low

A novel system for fully automated creation of layout, documentation and test programs for electrical test structures

Modern semiconductor processes have increasing complexity and thus an extremely high number of degrees of freedom. During the development of such a process a large number of test structures are necessary to understand the interaction of process parameters. In this paper we present a new method to streamline the information flow from development to layout and test.