Martin Knaipp

Investigations on the high current behavior of lateral diffused high-voltage transistors

This paper describes the high current behavior of a lateral, n-channel, high-voltage transistor. The starting points are TCAD experiments where the phenomenological behavior is analyzed. Based on these results a transistor high current model is derived, which is based on the vertical integrated free carrier concentration in the drift region. The important model parameter is the gate voltage, which defines the boundary condition for the free electron concentration at the beginning of the drift region. Because of the coupling of the carrier continuity equation and the Poisson equation (drift-diffusion model), this boundary condition plays a major role, and defines the carrier concentration inside the drift region. Together with an intrinsic low-voltage transistor model (intrinsic NMOS transistor), a series network is solved numerically. The network behavior reflects the TCAD experiments quite well and covers the different electrical regimes (the on-resistance regime, the quasi-saturation regime, and the saturation regime). The model output is compared with the TCAD experiments and the measured transistor data as well.

Investigations on an Isolated Lateral High-Voltage n-channel LDMOS Transistor with a Typical Breakdown of 150V

This work describes a concept of an isolated high-voltage (HV) n-channel LDMOS transistor, which can be used as a high-side switch instead of a HV PMOS transistor. HV n-channel LDMOSFETs for 120V applications (blocking voltage over 150V) were used in the study. The devices were fabricated in a 0.35 mum CMOS-based HV technology. Hot carrier stress experiments (under gate voltage VGS = 10V and drain voltage VD = 120V) were performed for device reliability evaluations. The devices with non-uniformly optimized n-well show an excellent trade-off between blocking voltage (BV) and on-resistance while keeping hot carrier induced degradation low

Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors

With the continuing scaling of metal–oxide–semiconductor (MOS) devices, the hot-carrier (HC)-induced device degradation has become a major reliabiliy concern in sub- and deep-submicrometre MOS field-effect transistors (MOSFETs) and lateral double-diffused MOSFETs (LDMOSFETs). It is believed that the degradation is mainly due to the effects of the generated oxide-trapped charges and interface traps at the Si/SiO2 interface. In general, the large electric field is strongly localised in a well-defined region; therefore carrier injection and interface-trap creation are similarly concentrated. The strongly inharmonious characters of HC injection and resulting damage present a considerable challenge to both experimental and modelling efforts.The HC degradation behaviour of an n-channel LDMOS transistor is investigated under various stress conditions. By applying variable base charge pumping experiments, a consistent picture of the degradation mechanism can be depicted. HC-induced interface traps are generated in the channel region of the device, in the drift region below the thick field oxide and at the birds beak edge. The latter is shown to dominate the degradation of Idlin, which is the most critical parameter concerning HC lifetime in this specific device.

Device Simulator Calibration for Quartermicron CMOS Devices

We present the calibration of a device simulator for a 0.25 µm CMOS technology using response surface methodology. For this process several measurements for different gate lengths (0.2–4.0 µm) were made. Care was taken to eliminate the statistical variations typical to sub-micron devices by measuring several chips on the the same wafer and taking an average sample. The simulations carried out with the calibrated parameters show an error smaller than 2.4% for both the long-channel and the short-channel device.

Drift design impact on quasi-saturation & HCI for scalable N-LDMOS

In this paper, we discuss the scalable NLDMOS design in a 0.18μm HV-CMOS technology. The design impacts in quasi-saturation are compared between the 25V and 50V NLDMOS to demonstrate the implications in output and fT characteristics. The STI depth sensitivity in DC, ac and HCI characteristics is investigated. The results prove a very robust design, featuring <10% Idlin shift over 10 year lifetime for +/−10% STI depth variations.

Hydrodynamic modeling of avalanche breakdown in a gate overvoltage protection structure

Abstract The breakdown of an overvoltage protection structure is analyzed in the temperature range from 298 to 523 K. The avalanche generation rates are modeled as a function of the carrier and lattice temperature. The generation rates are proportional to the carrier concentration. Careful attention is given to the pre-breakdown regime and to the breakdown process. The importance of various generation processes to the impact process is studied as well as the influence on variations of the ionization threshold energy and of the energy loss during the impact process. It is shown that the carrier generation inside the junction causes adiabatic carrier cooling, which leads to different carrier heating effects at low and high lattice temperature. The behavior of carrier heating at room temperature is strongly affected by the asymmetric field distribution inside the junction. The reason for this is the field dependence of the used trap assisted band to band tunneling model and of the direct band to band tunneling model. It is shown that at room temperature, the onset of hole impact ionization plays an important role for the electron heating. This is different at a temperature of 523 K, where the electrons dominate the onset of impact ionization.

Hot-carrier behaviour and ron-BV trade-off optimization for p-channel LDMOS transistors in a 180 nm HV-CMOS technology

This work reports the hot-carrier (HC) behavior and specific on-resistance (Ron,sp) optimization of 20~60 V p-channel LDMOS transistors implemented in a 180 nm HV-CMOS technology. By precise control the implant dose and energy of a p-drift region, which is surrounded by n-type isolation well, one can efficiently optimize the on-resistance and breakdown voltage (BV) trade-off while keeping very low HC degradation. Both of the TCAD simulations and measurements are described to explain the proposed technology and the transistor behaviour. Reported p-channel LDMOS transistor (pLDMOS) shows a very low HC-induced degradation - percent change of linear region of drain current (Idlin) below 3 % till 1×105 sec stress), and it shows an excellent Ron,sp-BV trade-off (pLDMOS with 20V GOX: BV = -85 V and Ron,sp = 1.64 mΩ-cm2).

A novel system for fully automated creation of layout, documentation and test programs for electrical test structures

Modern semiconductor processes have increasing complexity and thus an extremely high number of degrees of freedom. During the development of such a process a large number of test structures are necessary to understand the interaction of process parameters. In this paper we present a new method to streamline the information flow from development to layout and test.

Two-Dimensional Simulation of Ferroelectric Nonvolatile Memory Cells

An approach to increase the capabilities of integrated circuit nonvolatile memory is to take advantage of the hysteresis in the polarization of ferroelectric materials. For a rigorous analysis of this and similar devices a suitable model for the ferroelectric effects has been developed. We describe this model and show the results of its implementation into a device simulator.

Optimization of Industrial High Voltage Structures by Three-Dimensional Diffusion Simulation

A major goal in the process development of high voltage processes is the design of devices with given breakdown voltages and low switch on resistances. To reach this goal it is necessary to optimize the space charge regions of the device. Unfortunately these effects are three-dimensional and a device optimization needs the support of accurate three-dimensional simulation, which is shown in this article.