Jong Mun Park

Interface traps density-of-states as a vital component for hot-carrier degradation modeling

We refine our approach for hot-carrier degradation modeling based on a thorough evaluation of the carrier energy distribution by means of a full-band Monte–Carlo simulator. The model is extended to describe the linear current degradation over a wide range of operation conditions. For this purpose we employ two types of interface states, either created by single- or by multiple-electron processes. These traps apparently have different densities of states which is important to consider when calculating the charges stored in these traps. By calibrating the model to represent the degradation of the transfer characteristics, we extract the number of particles trapped by both types of interface traps. We find that traps created by the single- and multiple-electron mechanisms are differently distributed over energy with the latter shifted toward higher energies. This concept allows for an accurate representation of the degradation of the transistor transfer characteristics.

Physics-Based Hot-Carrier Degradation Modeling

We present a thorough analysis of physics-based hot-carrier degradation (HCD) models. We discuss the main features of HCD such as its strong localization at the drain side of the device, the weakening of the degradation at higher temperatures, and the change of the worst-case condition in small devices. The first feature is related to “hot” carriers, while the second is controlled by the fraction of “colder” particles. The latter feature is related to the change of the silicon-hydrogen bondbreakage mechanism from the singleto multiple-carrier process. All these findings suggest that the interface state creation process is controlled by the manner how the carriers are distributed over energy, that is, by the carrier energy distribution function. We distinguish between three main aspects of the physical picture behind hot-carrier degradation: carrier transport, microscopic mechanisms of defect creation and simulation of degraded devices. Therefore, we analyze and classify the existing HCD models in this context. Finally we present our hot-carrier degradation model based on a thorough evaluation of this distribution function by means of a full-band Monte-Carlo device simulator. Our approach tries to address the whole hierarchy of physical phenomena in order to capture all the essential aspects of hot-carrier

Investigations on an Isolated Lateral High-Voltage n-channel LDMOS Transistor with a Typical Breakdown of 150V

This work describes a concept of an isolated high-voltage (HV) n-channel LDMOS transistor, which can be used as a high-side switch instead of a HV PMOS transistor. HV n-channel LDMOSFETs for 120V applications (blocking voltage over 150V) were used in the study. The devices were fabricated in a 0.35 mum CMOS-based HV technology. Hot carrier stress experiments (under gate voltage VGS = 10V and drain voltage VD = 120V) were performed for device reliability evaluations. The devices with non-uniformly optimized n-well show an excellent trade-off between blocking voltage (BV) and on-resistance while keeping hot carrier induced degradation low

Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors

With the continuing scaling of metal–oxide–semiconductor (MOS) devices, the hot-carrier (HC)-induced device degradation has become a major reliabiliy concern in sub- and deep-submicrometre MOS field-effect transistors (MOSFETs) and lateral double-diffused MOSFETs (LDMOSFETs). It is believed that the degradation is mainly due to the effects of the generated oxide-trapped charges and interface traps at the Si/SiO2 interface. In general, the large electric field is strongly localised in a well-defined region; therefore carrier injection and interface-trap creation are similarly concentrated. The strongly inharmonious characters of HC injection and resulting damage present a considerable challenge to both experimental and modelling efforts.The HC degradation behaviour of an n-channel LDMOS transistor is investigated under various stress conditions. By applying variable base charge pumping experiments, a consistent picture of the degradation mechanism can be depicted. HC-induced interface traps are generated in the channel region of the device, in the drift region below the thick field oxide and at the birds beak edge. The latter is shown to dominate the degradation of Idlin, which is the most critical parameter concerning HC lifetime in this specific device.

Analysis of hot carrier effects in a 0.35 μm high voltage n-channel LDMOS transistor

This paper presents the results of hot carrier stress experiments of a high voltage 0.35 μm n-channel lateral DMOS transistor. The stress induced degradation was investigated at different ambient temperatures over a wide range of both gate- and drain-stress voltages. In order to explain the observed device degradation under these stress conditions, the combined influence of hole- and electron induced degradation have to be taken into account. A physical explanation of the observed effects is provided and a phenomenological degradation model is suggested.

Hot-carrier behaviour and ron-BV trade-off optimization for p-channel LDMOS transistors in a 180 nm HV-CMOS technology

This work reports the hot-carrier (HC) behavior and specific on-resistance (Ron,sp) optimization of 20~60 V p-channel LDMOS transistors implemented in a 180 nm HV-CMOS technology. By precise control the implant dose and energy of a p-drift region, which is surrounded by n-type isolation well, one can efficiently optimize the on-resistance and breakdown voltage (BV) trade-off while keeping very low HC degradation. Both of the TCAD simulations and measurements are described to explain the proposed technology and the transistor behaviour. Reported p-channel LDMOS transistor (pLDMOS) shows a very low HC-induced degradation - percent change of linear region of drain current (Idlin) below 3 % till 1×105 sec stress), and it shows an excellent Ron,sp-BV trade-off (pLDMOS with 20V GOX: BV = -85 V and Ron,sp = 1.64 mΩ-cm2).

Cost Effective High-Voltage IC Technology Implemented in a Standard CMOS Process

For competitive high-voltage (HV) integrated circuit (IC) products an excellent trade-off between specific on-resistance Ron,sp and breakdown voltage BV of a HV lateral DMOS (LDMOS) transistor, while keeping low fabrication cost, is mandatory. This paper presents a review of the HVIC technology trend with special emphasis on cost effective 0.35 μm and 0.18 μm HV-CMOS technologies. Through optimized process setup and device engineering a very competitive Ron,sp-BV trade-off of a HV LDMOS transistor without degrading the low-voltage (LV) CMOS performance has been achieved. A 0.35μm HV-CMOS technology with LDMOS transistor operating voltages from 20V to 120V is reported. Only two mask level adders on top of standard CMOS are required to provide the full set of 3.3V, 5V and 20V-120V HV devices. This is the result of taking advantage of predictive TCAD which enables early optimization of device layouts and dopant concentrations. In addition, HV and LV process integration issues of a 0.18 μm HV-CMOS technology, which play a key role to efficiently implement a HV module into a deep submicron CMOS process, are described. Key issues of p-channel LDMOS transistors are reviewed. The hot-carrier (HC) behaviour of a 50 V p-channel LDMOS transistor is presented too.

High-voltage lateral trench gate SOI-LDMOSFETs

We present a lateral trench gate SOI-LDMOSFET that uses narrow trenches as channels. The lateral trench gate, which allows the channel current to flow laterally on the trench side walls, decreases its on-resistance because it increases the current spreading area of the device. The specific on-resistance ðRspÞ strongly depends on the trench depth, which affects the channel area on the side wall of the trench and the space between the trenches affects the channel density of the device. The Rsp of the suggested devices as a function of the lateral trench depth and the space between the trenches are studied. Three-dimensional numerical simulations with MINIMOS-NT have been performed to investigate the influence of device parameters on the Rsp and the breakdown voltage. The improvement in the current handling capability of the suggested device is about 8.3% compared to the conventional SOI-LDMOSFET. q 2003 Elsevier Ltd. All rights reserved.

A method for generating structurally aligned grids for semiconductor device simulation

The quality of the numeric approximation of the partial differential equations governing carrier transport in semiconductor devices depends particularly on the grid. The method of choice is to use structurally aligned grids since the regions and directions therein that determine device behavior are usually straightforward to find as they depend on the distribution of doping. Here, the authors present an algorithm for generating structurally aligned grids including anisotropy with resolutions varying over several orders of magnitude. The algorithm is based on a level set approach and permits to define the refined resolutions in a flexible manner as a function of doping. Furthermore, criteria on grid quality can be enforced. In order to show the practicability of this method, the authors study the examples of a trench gate metal-oxide-semiconductor field-effect transistor (TMOSFET) and a radio frequency silicon-on-insulator lateral double diffused metal-oxide-semiconductor (RF SOI LDMOS) power device using the device simulator MINIMOS NT, where simulations are performed on a grid generated by the new algorithm. In order to resolve the interesting regions of the TMOSFET and the RF SOI LDMOS power device accurately, several regions of refinement were defined where the grid was grown with varying resolutions.

TCAD study of Single Photon Avalanche Diode on 0.35μm high voltage technology

This paper presents the electrical and optical behavior of Single Photon Avalanche Diode. Key parameters as reverse breakdown voltage, spectral responsivity, photon detection probability, dark count rate and time delay of the diode are extracted from dedicated TCAD simulations.