George A. Brown

A new MOS radiation-induced charge: negative fixed interface charge

The irradiation behavior (up to approximately 1.3 Mrad (SiO/sub 2/)) of MOS capacitors (50-nm-thick dry-grown SiO/sub 2/, Al, or poly-Si gate) with or without postoxidation annealing (POA) in Ar at 1000 degrees C has been studied by conventional capacitance-voltage (C-V) analysis and thermally stimulated current techniques. The most important finding is that all of the samples processed for radiation hardness, i.e., without POA, exhibited a charge compensation effect. The radiation-induced positive oxide charge is partially compensated by a negative fixed interface charge that either lies outside the energy range accessible by C-V and similar techniques or extends spatially away from the interface into the oxide without acquiring the characteristics of a bulk oxide charge. >

Deuterium interactions with ion‐implanted SiO2 layers in silicon

The interactions of deuterium gas (D2) with implantation‐formed Si‐SiO2‐Si structures were investigated in the temperature range 500–1000u2009°C using nuclear‐reaction analysis. At 600u2009°C and above there is substantial permeation of D through the overlying Si layer, and this D becomes stably bound within the buried SiO2. The reactions within the implantation‐formed oxide differ significantly from those in thermal oxides and are characterized by two distinct time regimes. In the first regime there is a rapid transient reaction which, at least at 600u2009°C, is controlled by permeation through the Si overlayer. After the initial transient there is a much slower reaction within the oxide, prominent at 700u2009°C and higher, which is controlled by a reaction barrier. The results indicate that the implantation‐formed oxides contain more numerous hydrogen‐reactive sites than do silica or thermal oxides on Si, and further that the number of these sites is substantially increased by Si epitaxial deposition. Deuterium permeat...

The polarity, field and fluence dependence of interface trap generation in thin silicon oxide

Abstract The interface trap generation in thin silicon oxide (SiO) during high-voltage stressing has been measured for oxides fabricated on p- and n-type substrates as a function of stress polarity, field and fluence. The generation of midgap interface traps was independent of stress polarity and substrate type and was dependent on the fluence of electrons through the oxide modulated by the stress voltage. The interface trap generation rate varied as (fluence) − 1 2 . Generation rates of midgap interface traps as high as 1016 states eV−1C−1 were measured at low fluences with the generation rate dropping to 1012 states eV−1C−1 at high fluences as the oxide approached breakdown. The large variation in the interface trap generation rate suggested that high-voltage stress measurements may not be easily extrapolated to lower operating voltages. It has been proposed that the decrease in the trap generation rates as the fluence increased was due to the variable energies required for the breaking of bonds at the silicon-oxide interface. The polarity independence of the interface trap generation was in contrast to the polarity dependence observed in breakdown of SiO. Thus, breakdown in SiO was not correlated with interface trap generation.

Polarity dependence of thin oxide wearout

The properties of less than 10-nm-thick silicon oxide films have been measured as a function of substrate type, oxide thickness, stress polarity, stress voltage, geometry, and fluence to help define the physical processes involved in wearout and breakdown. Changes that have been observed in the I-V, I-t, and C-V characteristics of 10-nm-thick oxides on p-type substrates as a function of stress and measurement polarity are reported. The differences in trap generation and charge trapping that occur during and following the high-voltage stressing of thin oxides are discussed. >

Extrapolation of high-voltage stress measurements to low-voltage operation for thin silicon-oxide films

Breakdown and wearout in MOS capacitors fabricated with 10 nm-thick silicon oxide films on p-type silicon are discussed. They have been stressed at high voltages. The high-voltage-stress-induced changes in the oxide properties are extrapolated to low operating voltages. The stress voltages ranged from -7.5 V to -14.5 V. The fluence during the stress was systematically varied front 2*10/sup -5/ C/cm/sup 2/ to 6 C/cm/sup 2/ by varying the stress time at each voltage. The number of interface traps generated by the stress increased as the stress voltage and fluence increased. However, the interface trap generation rate decreased as the fluence increased. The trap generation rate at low operating voltages was very high, but because the current through the oxide was small, the total number of traps generated was low. The trap generation rate was proportional to the inverse square root of the fluence with a voltage dependence that decreased as the fluence increased. Extrapolation of the high-voltage-stress measurements to 5 V shows that easily detectable changes in the oxide properties would only occur after several years of 5 V operation. Extrapolation of charge-to-breakdown and time-to-breakdown data to 5 V operation indicates that breakdown would occur after hundreds of years of device operation. >

Generation of thermally induced defects in buried SiO2 films

We show that annealing of the buried oxide layer used for device isolation generates point defects in the SiO2 film and that this defect generation is independent of temperature above 1000u2009°C. Electron paramagnetic resonance data obtained on thermally grown buried oxides and those fabricated by ion implantation indicate that the defect is intrinsic to the structure of SiO2 and is associated with an oxygen deficient environment. The similarity in the generation of the defects studied here and the formation of SiO observed in earlier studies of low pressure high temperature oxidation suggests that the formation of the buried oxide defect is related to the reduction of SiO2 and the release of SiO.

Remote plasma nitrided oxides for ultrathin gate dielectric applications

Two major concerns for ultrathin gate dielectric films have emerged with device scaling for CMOS devices: (1) B penetration in PMOS devices from the p+ boron-doped gate electrodes into the oxide and the underlying Si, (2) and increase in gate leakage current with decreasing oxide thickness. Oxynitride, nitride, and stacked nitride-oxide gate dielectrics have been proposed to overcome the above hurdles. Remote-plasma nitrided oxides (RPNO), involving nitridation of thermally grown oxides with a remote high-density nitrogen discharge, have emerged as promising candidates for ultrathin gate dielectric applications. These dielectrics are comprised of a thin layer of uniform and high N concentration at the poly/dielectric interface for an effective barrier to suppress B diffusion, and do not show the typical mobility and transconductance degradation observed (particularly in PMOS devices) with thermally grown oxynitride and nitride films. No increase in defect tail populations is observed from the nitridation. For stacked nitride-oxide films formed with this approach, a 10X reduction in gate leakage current is observed for Tox,eqapproximately 2 nm. In applications involving metal gate electrodes, the RPNO films show significant reliability improvements over conventional oxides, attesting to potential advantages in preventing detrimental gate electrode/dielectric interactions. The potential advantages of such a gate dielectric scaling approach lie in: (1) the ability to start with a relatively thicker oxide where thickness targeting and process control is easier, (2) an essentially self-limiting process leading to built-in uniformity of that of starting oxide, (3) the ability to control the thickness of the nitride layer and the spatial distribution of N, (4) adaptability/flexibility for integration with conventional oxide processing including cluster-tool processing, and (5) potential for scalability beyond the 0.10 micrometer technology node.

Defect electrical conduction in SIMOX buried oxides

It is pointed out that the buried oxide (BOX) layers in SIMOX structures exhibit localized defect conduction superimposed on the background (bulk) conduction. Type I defects show a pre-breakdown quasi-linear I-V characteristic with 10/sup -7/ >

Bulk trap formation by high temperature annealing of buried thermal oxides [SIMOX]

The formation of electron and hole traps has been investigated in thermally grown silicon dioxide that was encapsulated by polysilicon and annealed at temperatures ranging from 1100 to 1325/spl deg/C. Three buried oxide thicknesses have been examined: 25, 100 and 400 nm. Using the cryogenic detrapping technique, trapping of holes and electrons in traps up to 2 eV deep (tunneling depth) has been measured. The dependence of trap formation on the oxide thickness and annealing temperature suggest that the oxygen deficiency responsible for trap formation is diffusion limited and the formation rate is consistent with the SiO diffusion data published by Cellers et al. [1989]. In addition to the shallow electron trap at 1 eV, a deeper electron trap at 1.7 eV that remains occupied at room temperature is present during the early stages of oxygen depletion. Once the formation of electron traps has saturated, the deeper trap is not observed. During irradiation, the ratio of the number of electrons captured in traps or recombining with trapped holes to the number escaping the oxide is affected by the oxide thickness. The effect of the oxide thickness on the retention of electrons within the oxide is discussed. TEM micrographs show within the polysilicon during the interface between the polysilicon and oxide, but no effect on charge trapping has been observed.

Measurement of Low-Energy X-Ray Dose Enhancement in MOS Devices with Metal Silicide Gates

A photocurrent technique was used to accurately measure dose enhancement in the gate oxide of MOS devices with tungsten or titanium silicide over various thicknesses of poly-Si exposed to low-energy x-irradiation. The results show that the dose enhancement is strongly dependent on the type of metal/silicide used and the thickness of the poly-Si layer between the metal/silicide and the SiO2 gate insulator. A straightforward procedure for calculating the equal damage dose equivalence for metal/silicide over poly-Si gate MOS structures is also presented.