George Anthony Sai-Halasz

CMOS scaling into the nanometer regime

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFETs, low-temperature CMOS, and double-gate MOSFETs, which may lead to the outermost limits of silicon scaling.

High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level

Transport properties are investigated in self-aligned NMOS devices with gate lengths down to 0.07 mu m. Velocity overshoot was observed in the form of the highest transconductances measured to date in Si FETs, as well as in the trend of the transconductance with gate length. The measured transconductance reached 910 mu S/ mu m at liquid-nitrogen temperature and 590 mu S/ mu m at room temperature. Velocity overshoot, by making such transconductances possible, should extend the value of miniaturization to dimensions that are smaller than what was commonly assumed to be worthwhile to pursue.<<ETX>>

VLSI on-chip interconnection performance simulations and measurements

We examine electrical performance issues associated with advanced VLSI semiconductor on-chip interconnections or “interconnects.” Performance can be affected by wiring geometry, materials, and processing details, as well as by processor-level needs. Simulations and measurements are used to study details of interconnect and insulator electrical properties, pulse propagation, and CPU cycle-time estimation, with particular attention to potential advantages of advanced materials and processes for wiring of high-performance CMOS microprocessors. Detailed performance improvements are presented for migration to copper wiring, low-e dielectrics, and scaled-up interconnects on the final levels for long-line signal propagation.

Shallow p+ junction formation by a reverse‐type dopant preamorphization scheme

Device grade ultrashallow p+ junctions have been fabricated by a novel ion implantation scheme. The novelty of the method is in using antimony to amorphize silicon prior to a low‐energy boron implantation. Antimony satisfies a combination of two requirements lacking from all previously applied preamorphization schemes. First, due to the heavy mass of antimony, amorphization of silicon is achieved with a minimal amount of implantation damage. Second, and most important, antimony is a dopant of an opposite type than boron. Because of this, the inevitable implant tail of the preamorphizing species serves to confine the depth of the p layer. The optimized conditions for the application of this scheme have been determined. Junctions below 100 nm in depth, with less than 200 Ω/⧠ sheet resistance and junction leakage of 10 nA/cm2, have been achieved. The electrical results have been correlated with the residual defect structure observed by cross‐sectional transmission electron microscopy.

Directions in future high end processors

Results based on a new cycle-time model are presented to demonstrate performance trends for complex bipolar ECL-CSEF and CMOS processors. It is shown that performance constraints are quite different for these two systems. For a given design the performance of a CMOS processor is tied to lithography, whereas future CSEF bipolar processors will be gated primarily by the power density capability of the package. Liquid nitrogen temperature (LN/sub 2/) CMOS is seen as having the potential to become the highest performance technology for mainframe uniprocessors.<<ETX>>

Effects of Indium Preamorphization on Boron Implanted Silicon Annealed by RTA

Preamorphization by indium of boron implanted silicon layers has been studied as a means of reducing defects in the annealed and activated shallow junctions. The In preamorphized samples after RTP annealing at 950 to 1150°C show an absence of spanning dislocations. A 5 sec. anneal at 1100 °C results in the complete annihilation of residual dislocation loops at the original crystalline/amorphous (c/a) interface. The minimum dose to preamorphize Si with 200keV In was 5×10 13 /cm 2 . During annealing the In was found to localize at two peaks, one at the original c/a interface and the other closer to the surface, where In precipitation was observed.

Enhanced Diffusion During Rapid Thermal Annealing Of Indium And Boron In Double Implanted Silicon

Experimental results on the diffusion and precipitation of In and B doubly implanted into Si, followed by rapid thermal treatment are reported. It was observed that In redistributes itself and accumulates in defected regions. The amount of motion of each species is enhanced by the presence of the other. While the B influences In diffusion probably through the same mechanism that leads to concentration enhancement, the effect of In on B is not clear. There is no correlation with strain and no apparent chemical effects. Also the presence of B facilitates the sweeping out of In during low temperature solid phase regrowth.

Formation of Shallow Boron P + Junctions Using Sb Amorphization

Shallow P + junctions have been fabricated using reverse-type dopant preamorphization by Sb. The junctions ∼100 nm in depth have leakage current below 10 nA/cm 2 , sheetresistance less than 200 Ω/□ and ideality factor in the range 1.01–1.03. This type of amorphization scheme provides electrical activation of B at low temperature, which is very promising for low temperature processing applications. The importance of process optimization was demonstrated. The electrical results were correlated with residual defect structure observed by cross-sectional TEM.